Abstract: A method of fabricating a one-time programmable read only memory (OTP-ROM) with reduced size is disclosed. In accordance with the method of the present invention, a stacked structure is formed on a substrate. The stacked structure comprises a first oxide layer, a first polysilicon layer, and a second oxide layer formed in sequence on the substrate. The substrate beside the stacked structure is exposed by the stacked structure. An implanted region is formed in the exposed substrate beside the stacked structure. A spacer is formed on a sidewall of the stacked structure. A silicide layer is formed on the implanted region. A silicon nitride layer is formed to cover the second oxide layer, the spacer, and the silicide layer. A second polysilicon layer is formed to cover the silicon nitride layer. The second polysilicon layer is patterned to form a control gate. The first polysilicon layer is further patterned to form a floating gate.

Abstract: A flash memory. An oxide layer is on a substrate. A stacked gate is formed on the substrate. A tunnel diffusion region is formed in the substrate next to a first side of the stacked gate. The tunnel diffusion region extends to a portion of the substrate under the stacked gate. A doped region is formed in the substrate next to a second side of the stacked gate. The doped region is distant away from the stacked gate by a lateral distance. An inter-poly dielectric layer covers the tunnel diffusion region, the doped region, and the stacked gate. A polysilicon layer is on the inter-poly dielectric layer and extends perpendicular to the stacked gate.

Abstract: A flash memory. A tunnel oxide layer covers a part of a substrate. The tunnel oxide layer is covered by a floating gate. A first inter-poly dielectric layer is on the floating gate. A controlling gate is on the first inter-poly dielectric layer and extending in a strip shape along a first direction. A second inter-poly dielectric layer covers a first side wall of the floating gate, the first inter-poly dielectric layer, and the controlling gate. A polysilicon spacer is formed covering the second inter-dielectric layer. A drain region is next to a second side wall of the floating gate the first interpoly dielectric layer. and the controlling gate in the substrate. A source region is next to the spacer in the substrate. A select gate covering the controlling gate, the tunnel oxide layer. and the spacer extends along a second direction perpendicular to the first direction.

Abstract: A flash memory. An oxide layer is on a substrate. A stacked gate is formed on the substrate. A tunnel diffusion region is formed in the substrate next to a first side of the stacked gate. The tunnel diffusion region extends to a portion of the substrate under the stacked gate. A doped region is formed in the substrate next to a second side of the stacked gate. The doped region is distant away from the stacked gate by a lateral distance. An inter-poly dielectric layer covers the tunnel diffusion region the doped region, and the stacked gate. A polysilicon layer is on the inter-poly dielectric layer and extends perpendicular to the stacked gate.

Abstract: A method of forming mixed mode devices is provided. A field oxide layer is formed on the substrate to isolate active regions from each other. A gate oxide layer is formed on the substrate, positioned over the active regions. A first conductive layer, a silicide layer and a second conductive layer are formed on the field oxide layer and on the gate oxide layer. The second conductive layer is converted to an oxide layer as a dielectric layer of a capacitor by thermal oxidation. A third conductive layer is formed and defined on the dielectric layer to form an upper electrode of the capacitor. A anisotropic etching step is performed to remove a part of the dielectric layer, a part of the silicide layer and a part of the first conductive layer to complete the capacitor and to form a gate of a transistor.

Abstract: A flash memory comprises a plurality of word lines, a plurality of source lines and a plurality of bit lines, the word lines are arranged in a matrix with the bit lines and the source lines, respectively. Between every two adjacent bit line and source line and on every word line there forms a memory cell. Each bit line and source line are coupled to memory cells of two columns. During the procedure of "erase", two columns of memory cells can be erased at the same time. Methods of programming, erasing and reading the flash memory are much easy and controllable.

Abstract: A method for fabricating a flash memory forms a diffusion region in the substrate at one side of the first polysilicon layer. Formation of the diffusion region is preceded by a number of steps. First, the first polysilicon layer is patterned. Then, an implantation step is performed to self-align the polysilicon layer, thereby forming implantation regions in the substrate at both sides of the first polysilicon. One of these implantation region is used for a buried bit line. Subsequently, a dielectric layer is formed over the first polysilicon layer, and the second polysilicon layer is patterned to form a control gate and the first polysilicon layer is further patterned to form a floating gate.

Abstract: The method includes forming a first insulating layer over a substrate. A first metal layer is formed over the first insulating layer. The first metal layer is patterned to form a plurality of parallel bit lines. A second insulating layer is formed over the bit lines and first insulating layer. At least one via is formed in the second insulating layer. Tungsten fills the via to form a tungsten plug. A second metal layer is formed over the second insulating layer. The second metal layer is patterned to form a plurality of parallel word lines. The word lines and the bit lines crosses at an angle. The present invention is also directed toward a high density ROM device that comprises a substrate and at least one memory array, including a first insulating layer located over a surface of the substrate, and a bit line located on a surface of the first insulating layer.

Abstract: A method for programming, reading and erasing data stored in a non-volatile memory, a flashing memory in particular, includes applying different voltages on individual components of a flash memory. The flash memory physically consists of a substrate, and a tunneling oxide layer, a floating gate, a dielectric layer and a control gate formed on the substrate in sequence, wherein the substrate also contains a source region and a drain region. A conformed dielectric layer and a selective gate further cover the forgoing structure. By applying properly selected voltages on the substrate, the source region, the drain region, the control gate and the selective gate, the method is capable of preventing the drawbacks of a conventional method on programming, reading and erasing data stored in a flash memory, and improving the process efficiency.

Abstract: A method for fabricating an OTP-ROM includes a first polysilicon layer formed over a semiconductor substrate. An ion implanting process is performed to form a diffusion region inside the substrate on both sides of the first polysilicon layer. This diffusion region acts as a bit line. Then, a second polysilicon layer is formed to cover the first polysilicon layer. The second polysilicon layer is patterned to form a control gate. The patterning process is continued to further pattern the first polysilicon layer to form a floating gate.

Abstract: A method of forming a ROM includes forming a pad oxide layer on a P-type substrate, forming a silicon nitride layer on the pad oxide layer and patterning the silicon nitride layer. An N well is formed in the P-type substrate, wherein some of the silicon nitride layer is over the N well. A field oxide layer is formed over the substrate. The silicon nitride layer is removed. The N well is doped using first P-type ions to form a plurality of essentially parallel P-pole regions. An insulating layer is formed over the field oxide layer. A plurality of contact windows are formed within the insulating layer to expose a portion of the P-pole regions. The N well is doped and annealed, to form a plurality of P-type diffusion regions under the exposed portions of the P-pole regions. The P-pole regions are doped and annealed, to form a plurality of N-type diffusion regions in the exposed portions of the P-pole regions. A metal layer is formed which fills the contact windows.

Abstract: A read only memory device, which includes a P-type substrate, is provided. Several essentially parallel N-pole regions are located on the substrate. The N-pole regions extends in a first direction, and are separated from each other by a space. The N-pole regions form bit lines. Several N-type diffusion regions are located under selected portions of respective N-pole regions. Several P-type diffusion regions are located over respective selected portions of the N-pole regions. Each respective P-type diffusion region and associated N-pole region forms a diode. Several essentially parallel word lines extend in a second direction. Each word line is separated from an adjacent word line by a space. Each of the word lines is coupled to each of the corresponding P-type diffusion regions.

Abstract: A method of forming low resistance contact structures in vias arranged between interconnect levels is provided. The method involves interconnect lines having an anti-reflective layer formed thereupon. An interlevel dielectric layer is formed over the interconnect lines. A photoresist layer is formed over the interlevel dielectric layer and patterned to define via locations. During via etch, an organic (carbon-based) polymer layer forms upon the anti-reflective-coated interconnect lines at the bottoms of the vias. The photoresist and the etch byproduct polymer layers are then removed using a dry etch process which employs a forming gas comprising nitrogen and hydrogen. A native oxide layer subsequently forms upon the anti-reflective-coated interconnect lines when exposed to oxygen. The native oxide layer is then removed, along with any residual etch byproduct polymer, during a sputter etch procedure.

Abstract: An isolation technique is provided for improving the overall planarity of filled isolation regions relative to adjacent silicon mesas. The isolation process results in a silicon mesa having enhanced mechanical and electrical properties. Planarity is performed by repeating the steps of filling isolation trenches, patterning large area isolation trenches, and refilling isolation trenches to present an upper surface having indents which can be readily removed by a chemical-mechanical polish. The silicon mesa upper surface is enhanced by utilizing a unique set of layers stacked upon the silicon substrate, and thereafter patterning the substrate to form raised silicon surfaces, or mesas, having the stacked layers thereon. The patterned, stacked layers include a unique combination of dissimilar compositions which, when removed, leave a silicon mesa upper surface which is recessed below the adjacent, filled trenches.

Abstract: A method of forming a self-aligned field oxide isolation structure without using silicon nitride. The method comprises forming a dielectric on an upper surface of a semiconductor substrate. The upper surface of the semiconductor substrate comprises an active region and an isolation region laterally adjacent to each other. A photoresist layer is patterned on top of the implant dielectric to expose regions of the implant dielectric over the active region. Nitrogen is then implanted into the active region through the implant dielectric. Nitrogen is preferably introduced into semiconductor substrate in an approximate atomic concentration of 0.5 to 2.0 percent. After the nitrogen has been implanted into a semiconductor substrate, the photoresist layer is stripped and the implant dielectric is removed. The wafer is then thermally oxidized such that a field oxide having a first thickness is grown over the isolation region and a thin oxide having a second thickness is grown over the active region.

Abstract: An oxide layer is thermally grown over a semiconductor body, and openings are etched in the oxide layer to expose portions of the surface of the semiconductor body. Then, epitaxial regions are grown from the semiconductor body into the openings in the oxide layer, which epitaxial regions will eventually become the active regions of devices.

Abstract: A method of forming a self-aligned field oxide isolation structure without using silicon nitride. The method comprises forming a dielectric on an upper surface of a semiconductor substrate. The upper surface of the semiconductor substrate comprises an active region and an isolation region laterally adjacent to each other. A photoresist layer is patterned on top of the implant dielectric to expose regions of the implant dielectric over the active region. Nitrogen is then implanted into the active region through the implant dielectric. Nitrogen is preferably introduced into semiconductor substrate in an approximate atomic concentration of 0.5 to 2.0 percent. After the nitrogen has been implanted into a semiconductor substrate, the photoresist layer is stripped and the implant dielectric is removed. The wafer is then thermally oxidized such that a field oxide having a first thickness is grown over the isolation region and a thin oxide having a second thickness is grown over the active region.

Abstract: A method for fabricating a one-time programmable read only memory includes forming a spacer to cover the sides of the periphery transistor gate before patterning the control gate, then patterning the polysilicon layer to form a floating gate, and then forming a heavily concentrated ion implantation area in the substrate beneath the sides of the floating gate. Since the spacer is deposited on the sidewalls of the polysilicon layer within the peripheral area, but not the memory cell area, the efficiency of programming is improved. In addition, there is no need for extra ion implantation processes for make up for the lower programming efficiency caused by the spacers. Furthermore, the leakage current that is caused by the damage to the field oxide generated during the etching back process for forming the spacer is eliminated.

Abstract: A read method for reading data from a ROM device is provided, which can be operated with a higher voltage to address the memory cells in the ROM device. The ROM device are formed with word and bit lines formed from metallization layers having a very low resistance so that the data current can be increased for increased performance. This read method is for use on a ROM device of the type including an array of memory cells formed at the intersections between a plurality of word lines and a plurality of bit lines. Of these memory cells, a first selected group are set to a permanently-ON state due to the forming of a contact window connecting the associated word line to the associated bit line, and a second selected group of the memory cells are set to a permanently-OFF state due to the forming of no contact window therein.

Abstract: A diode type read only memory (ROM) includes a diode as a memory cell. The diode is a logic level "on" memory cell and coupled to one of the word lines and one of the bit lines of the ROM. A relative high voltage is given to the bit line coupled to the diode and a relative high voltage is given to the corresponding word line. Therefore, the data saved in the diode can be read out.