Abstract: Programmable resistive RAM cells have a resistance that depends on the size of the contacts. Manufacturing methods and integrated circuits for lowered contact resistance are disclosed that have contacts of reduced size.

Abstract: A NAND-type flash memory device includes asymmetric floating gates overlying respective wordlines. A given floating gate is sufficiently coupled to its respective wordline such that a large gate (i.e., wordline) bias voltage will couple the floating gate with a voltage which can invert the channel under the floating gate. The inversion channel under the floating gate can thus serve as the source/drain. As a result, the memory device does not need a shallow junction, or an assist-gate. In addition, the memory device exhibits relatively low floating gate-to-floating gate (FG-FG) interference.

Abstract: A resistance type memory device is provided. The resistance type memory device includes a first and a second conductors and a metal oxide layer. The metal oxide layer is disposed between the first and the second conductors, and the resistance type memory device is defined in a first resistivity. The resistance type memory device is defined in a second resistivity after a first pulse voltage is applied to the metal oxide layer. The resistance type memory device is defined in a third resistivity after a second pulse voltage is applied to the metal oxide layer. The second resistivity is greater than the first resistivity, and the first resistivity is greater than the third resistivity.

Abstract: A memory device includes first and second electrodes separated by an insulating member comprising upwardly and inwardly tapering surfaces connected by a surface segment. A bridge, comprising memory material, such as a phase change material, switchable between electrical property states by the application of energy, is positioned across the surface segment and in contact with the electrodes to define an inter-electrode path defined at least in part by the length of the surface segment. According to a method for making a memory cell device, the tapering surfaces may be created by depositing a dielectric material cap using a high density plasma (HDP) deposition procedure. The electrodes and the dielectric material cap may he planarized to create the surface segment on the dielectric material. At least one of the dielectric material depositing step and the planarizing step may be controlled so that the length of the surface and segment is within a chosen dimensional range, such as between 10 nm and 100 nm.

Abstract: Memory devices and methods for operating such devices are described herein. A method as described herein for operating a memory device includes applying a sequence of bias arrangements across a selected metal-oxide memory element to change the resistance state from a first resistance state in a plurality of resistance states to a second resistance state in the plurality of resistance states. The sequence of bias arrangements comprise a first set of one or more pulses to change the resistance state of the selected metal-oxide memory element from the first resistance state to a third resistance state, and a second set of one or more pulses to change the resistance state of the selected metal-oxide memory element from the third resistance state to the second resistance state.

Abstract: A non-volatile memory with a self-aligned RRAM element includes a lower electrode element, generally planar in form, having an inner contact surface; an upper electrode element, spaced from the lower electrode element; a containment structure extends between the upper electrode element and the lower electrode element, with a sidewall spacer element having a generally funnel-shaped central cavity with a central aperture; and a spandrel element positioned between the sidewall spacer element and the lower electrode. A RRAM element extends between the lower electrode element and the upper electrode, occupying at least a portion of the sidewall spacer element central cavity and projecting from the sidewall spacer terminal edge toward and making contact with the lower electrode. In this manner, the spandrel element inner surface is spaced from the RRAM element to define a thermal isolation cell adjacent the RRAM element.

Abstract: A magnetic random access memory (MRAM) and a manufacturing method and a programming method thereof are provided. The magnetic random access memory comprises a first magnetic tunnel junction structure and a second magnetic tunnel junction structure The second magnetic tunnel junction structure is electrically connected with the first magnetic tunnel junction structure, and the volume of the second magnetic tunnel junction structure is smaller than that of the first magnetic tunnel junction structure.

Abstract: A non-volatile method with a self-aligned RRAM element. The method includes a lower electrode element, generally planar in form, having an inner contact surface. At the top of the device is a upper electrode element, spaced from the lower electrode element. A containment structure extends between the upper electrode element and the lower electrode element, and this element includes a sidewall spacer element having an inner surface defining a generally funnel-shaped central cavity, terminating at a terminal edge to define a central aperture; and a spandrel element positioned between the sidewall spacer element and the lower electrode, having an inner surface defining a thermal isolation cell, the spandrel inner walls being spaced radially outward from the sidewall spacer terminal edge, such that the sidewall spacer terminal edge projects radially inward from the spandrel element inner surface.

Abstract: A method for manufacturing a memory device comprises patterning a dielectric layer and a conductive layer to align near the center of the top surface of a first contact drain plug and near the center of the top surface of a second contact drain plug. A first electrode is formed on the right sidewalls of the patterned dielectric layer and the conductive layer. A sidewall insulating member has a first sidewall surface and a second sidewall surface where the first sidewall surface of the sidewall insulating member is in contact with a sidewall of the first electrode. A second electrode is formed by depositing an electrode layer overlying the top surface of the sidewall insulating member and the second sidewall of the insulating member and isotropically etching the electrode layer to form the second electrode.

Abstract: A resistance type memory device is provided. The resistance type memory device is disposed on a substrate and includes a tungsten electrode, an upper electrode, and a tungsten oxide layer. The upper electrode is disposed on the tungsten electrode. The tungsten oxide layer is sandwiched between the tungsten electrode and the upper electrode.

Abstract: A memory device including a programmable resistive memory material is described along with methods for manufacturing the memory device. A memory device disclosed herein includes top and bottom electrodes and a multilayer stack disposed between the top and bottom electrodes. The multilayer stack includes a memory element comprising programmable resistive memory material and has a sidewall surface. An air gap is adjacent to the sidewall surface and self-aligned to the memory element.

Abstract: A manufacturing method for stacked, non-volatile memory devices provides a plurality of bitline layers and wordline layers with charge trapping structures. The bitline layers have a plurality of bitlines formed on an insulating layer, such as silicon on insulator technologies. The wordline layers are patterned with respective pluralities of wordlines and charge trapping structures orthogonal to the bitlines.

Abstract: A resistive random access memory including, an insulating layer, a hard mask layer, a bottom electrode, a memory cell and a top electrode is provided. The insulating layer is disposed on the bottom electrode. The insulating layer has a contact hole having a first width. The hard mask layer has an opening. A portion of the memory cell is exposed from the opening and has a second width smaller than the first width. The top electrode is disposed on the insulating layer and is coupled with the memory cell.

Abstract: A method of manufacturing a non-volatile semiconductor memory device includes forming a sub-gate without an additional mask. A low word-line resistance is formed by a metal silicide layer on a main gate of the memory device. In operation, application of a voltage to the sub-gate forms a transient state inversion layer that serves as a bit-line, so that no implantation is required to form the bit-line.

Abstract: A memory and a manufacturing method thereof are provided. The memory includes a dielectric layer, a polysilicon layer, a first buried diffusion, a second buried diffusion, a charge storage structure and a gate. The polysilicon layer is disposed on the dielectric layer and electrically connected to at least a voltage. The first buried diffusion and the second buried diffusion are separately disposed in the surface of the polysilicon layer. The charge storage structure is disposed on the polysilicon layer and positioned between the first buried diffusion and the second buried diffusion. The gate is disposed on the charge storage structure.

Abstract: A magnetic memory device comprises a magnetic memory cell that includes a pinned layer and a free layer separated from the pinned layer by an insulating layer. The magnetic memory device also comprises a thermal plate in contact with the free layer. The magnetic memory device can be configured so that a first current flows through the thermal plate heating the thermal plate. The magnetic behavior of the free layer can be altered due to the heating caused by the first current, making it easier to switch the orientation and magnetization of the free layer. A second current can then flow through a bit line near the free layer generating a magnetic field sufficient to switch the orientation of magnetization of the free layer.

Abstract: A memory cell device, of the type that includes a memory material switchable between electrical property states by application of energy, includes first and second electrodes, a plug of memory material (such as phase change material) which is in electrical contact with the second electrode, and an electrically conductive film which is supported by a dielectric form and which is in electrical contact with the first electrode and with the memory material plug. The dielectric form is wider near the first electrode, and is narrower near the phase change plug. The area of contact of the conductive film with the phase change plug is defined in part by the geometry of the dielectric form over which the conductive film is formed. Also, methods for making the device include steps of constructing a dielectric form over a first electrode, and forming a conductive film over the dielectric form.

Abstract: A memory device comprises first and second electrodes with a memory element and a buffer layer located between and electrically coupled to them. The memory element comprises one or more metal oxygen compounds. The buffer layer comprises at least one of an oxide and a nitride. Another memory device comprises first and second electrodes with a memory element and a buffer layer, having a thickness of less than 50 ?, located between and electrically coupled to them. The memory comprises one or more metal oxygen compounds. An example of a method of fabricating a memory device includes forming first and second electrodes. A memory, located between and electrically coupled to the first and the second electrodes, is formed; the memory comprises one or more metal oxygen compounds and the buffer layer comprises at least one of an oxide and a nitride.

Abstract: A process in the manufacturing of a resistor random access memory with a confined melting area for switching a phase change in the programmable resistive memory. The process initially formed a pillar comprising a substrate body, a first conductive material overlying the substrate body, a programmable resistive memory material overlying the first conductive material, a high selective material overlying the programmable resistive memory material, and a silicon nitride material overlying the high selective material. The high selective material in the pillar is isotropically etched on both sides of the high selective material to create a void on each side of the high selective material with a reduced length. A programmable resistive memory material is deposited in a confined area previously occupied by the reduced length of the poly, and the programmable resistive memory material is deposited into an area previously occupied by the silicon nitride material.

Abstract: A manufacturing method for stacked, non-volatile memory device provides a plurality of bitline layers and wordline layers with charge trapping structures. The bitline layers have a plurality of bitlines formed on an insulating layer, such as silicon on insulator technologies. The wordline layers are patterned with respective pluralities of wordlines and charge trapping structures, orthoganal to the bitlines.