Patents by Inventor Kuang-Yu Tang

Kuang-Yu Tang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060285588
    Abstract: A video encoder having an updateable quantization table for compressing a video information is proposed. The features are: the video encoder has a RAM to store the quantization table; the quantization table can be updated according to the special environments or user demands to change the choice standard of quantization.
    Type: Application
    Filed: June 21, 2005
    Publication date: December 21, 2006
    Inventors: Kuang-Yu Tang, Kuo-Chang Fu, Jen-chung Wang
  • Patent number: 6738956
    Abstract: The present invention generally relates to a circuit configuration of a chip and, more particularly to a circuit configuration of a chip with a graphic controller integrated and a method for testing such a circuit configuration, in which a test circuit is employed in a main control module such that a graphic controller is directly connected to a plurality of buses in a testing mode. Thus, the testing of the graphic controller is independent of the main controller module. Moreover, the testing requests are transmitted to the graphic controller by using frequency multiplying modes, and at least one multiplexer and at least one latch are used at the memory end, so that the required pin count for testing is lowered in the present invention.
    Type: Grant
    Filed: August 12, 2002
    Date of Patent: May 18, 2004
    Assignee: Via Technologies, Inc.
    Inventors: Jiing Lin, Hsuan-Yi Wang, Chun-Yi Wu, Kuang-Yu Tang
  • Publication number: 20030149948
    Abstract: The present invention generally relates to a circuit configuration of a chip and, more particularly to a circuit configuration of a chip with a graphic controller integrated and a method for testing such a circuit configuration, in which a test circuit is employed in a main control module such that a graphic controller is directly connected to a plurality of buses in a testing mode. Thus, the testing of the graphic controller is independent of the main controller module. Moreover, the testing requests are transmitted to the graphic controller by using frequency multiplying modes, and at least one multiplexer and at least one latch are used at the memory end, so that the required pin count for testing is lowered in the present invention.
    Type: Application
    Filed: August 12, 2002
    Publication date: August 7, 2003
    Inventors: Jiing Lin, Hsuan-Yi Wang, Chun-Yi Wu, Kuang-Yu Tang