Abstract: Methods and systems for a device interfacing with a computing system are provided. The device is configured to send an input/output status block (IOSB) and an interrupt message to the processor of a computing system interfacing upon completion of an operation. The device generates the interrupt message while the IOSB is waiting to be transmitted; and transmits the IOSB to the processor, followed by the interrupt message, using a same data path for both the IOSB and the interrupt message. Furthermore, the device is configured to detect a request from the processor of the computing system interfacing to clear an interrupt status maintained by the device at a hardware location; send a message to the processor to de-assert the interrupt status and in parallel, clear the hardware location to clear the interrupt status such that the computing system can transfer information to the device for a next operation.

Abstract: Method and system for sending data from a memory of a computing system interfacing with a device is provided. An input/output control block (IOCB) from the computing system for transferring the data from the memory of the computing system is received by the device. The device then allocates a plurality of DMA channels to the IOCB for transferring the data from the memory of the computing system when a number of pending input/output (I/O) requests when the IOCB is received is less than a number of available direct memory access (DMA) channels to receive the data from the memory of the computing system.

Abstract: A method and system for performing data integrity process is provided. The method includes selecting a cyclic redundancy code (“CRC”) mode from amongst append, validate and keep, and validate and remove mode. If the append mode is selected, then CRC is appended after each data block boundary. A CRC seed value is incremented for each data block providing a unique CRC value for each data block. If validate and keep mode is selected, then CRC accompanying any data is compared to CRC that may have been accumulated. If validate and remove mode is selected, then CRC is first validated and then CRC is removed before data is sent out. The system includes CRC logic that allows firmware running on an adapter to select one of plural CRC modes including append, validate and keep, and validate and remove mode.