Patents by Inventor Kuan-Hua Su

Kuan-Hua Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11923409
    Abstract: A semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers over the semiconductor substrate and connected to the source/drain feature, a gate portion between vertically adjacent channel layers, and an inner spacer between the source/drain feature and the gate portion and between adjacent channel layers. The semiconductor device further includes an air gap between the inner spacer and the source/drain feature.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Yu Lin, Wei-Yang Lee, Chia-Pin Lin, Tzu-Hua Chiu, Kuan-Hao Cheng, Wei-Han Fan, Li-Li Su, Wei-Min Liu
  • Patent number: 10268795
    Abstract: A method for timing optimization is disclosed. The method includes obtaining information on detour locations of a chip by performing a routing operation, establishing, through machine learning, a model that describes a relationship between an image map and the detour locations, generating predicted detour locations based on the model and the image map, determining the probability of detouring in a region of the predicted detour locations, determining a predicted detour net for a path in a region having a high probability of detour, and determining sensitivity of the path.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Yi-Lin Chuang, Chih-Tien Chang, Kuan-Hua Su, Szu-Ju Huang
  • Publication number: 20180307790
    Abstract: A method for timing optimization is disclosed. The method includes obtaining information on detour locations of a chip by performing a routing operation, establishing, through machine learning, a model that describes a relationship between an image map and the detour locations, generating predicted detour locations based on the model and the image map, determining the probability of detouring in a region of the predicted detour locations, determining a predicted detour net for a path in a region having a high probability of detour, and determining sensitivity of the path.
    Type: Application
    Filed: April 20, 2017
    Publication date: October 25, 2018
    Inventors: YI-LIN CHUANG, CHIH-TIEN CHANG, KUAN-HUA SU, SZU-JU HUANG
  • Patent number: 8927058
    Abstract: A photoresist coating process including a first step and a second step is provided. In the first step, a wafer is accelerated by a first average acceleration. In the second step, the wafer is accelerated by a second average acceleration. The first acceleration and the second acceleration are both larger than zero, and photoresist material is provided to the wafer only in the second step.
    Type: Grant
    Filed: July 7, 2008
    Date of Patent: January 6, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Shou-Wan Huang, Kuan-Hua Su
  • Publication number: 20100003403
    Abstract: A photoresist coating process including a first step and a second step is provided. In the first step, a wafer is accelerated by a first average acceleration. In the second step, the wafer is accelerated by a second average acceleration. The first acceleration and the second acceleration are both larger than zero, and photoresist material is provided to the wafer only in the second step.
    Type: Application
    Filed: July 7, 2008
    Publication date: January 7, 2010
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Shou-Wan Huang, Kuan-Hua Su