Abstract: A hand tool holder includes a holder body including a first face, a second face, a third face, and a fourth face. The holder body is provided with at least one first groove arranged on the second face and the third face. The at least one first groove includes a first recessed portion, a first connecting portion, and a first mounting portion which are connected to construct an L-shaped channel. The holder body is provided with at least one second mounting portion connected to the first connecting portion. The holder body is provided with a fifth face. The at least one second mounting portion has an opening connected to the fifth face. The first recessed portion has an opening connected to the fifth face.

Abstract: The present disclosure provides a method that includes providing a substrate having a N region for n-type field-effect transistors (nFETs) and a P region for p-type field-effect transistors (pFETs); forming a gate dielectric layer in the N region and the P region to wrap around channels vertically stacked; performing a dipole treatment to a first portion of the gate dielectric layer in the N region while a second portion of the gate dielectric layer in the P region remain untreated; depositing a P metal layer in the gate dielectric layer in both the P region and the N region; and forming a fill metal layer on the P metal layer in both the P region and the N region.

Abstract: A screwdriver rotating structure includes a main body, a driving member, two locking modules, a first elastic element, a control member, a fixed plate, two snap-fit members, a positioning element, and a second elastic element. The main body is provided with two first receiving grooves, a second receiving groove, a third receiving groove, two fourth receiving grooves, a recess, and a restriction portion. The driving member is provided with a ratchet portion and an annular groove. The fixed plate is provided with a pivot hole. The two snap-fit members are assembled with the main body and the driving member. Each of the snap-fit members is provided with a snap-fit block pivotally mounted in the annular groove, so that the driving member is pivotally mounted on the main body. Each of the snap-fit members has a third abutting face.

Abstract: A semiconductor structure includes a semiconductor fin protruding from a substrate; a gate structure engaging with the semiconductor fin. The semiconductor structure also includes an interlayer dielectric (ILD) layer disposed over the substrate and adjacent to the gate structure, where a top surface of the gate structure is below a top surface of the ILD layer; a first metal layer in direct contact with a top surface of the gate structure; a second metal layer disposed over the first metal layer, where the first metal layer is disposed on bottom and sidewall surfaces of the second metal layer, where the bottom surface of the second metal layer has a concave profile, and where the second metal layer differs from the first metal layer in composition; and a gate contact disposed over the second metal layer.

Abstract: A semiconductor device and method of forming is provided. The method includes forming a first work function metal layer around a first nanostructure in a fin disposed over a substrate, oxidizing at least a portion of the first work function metal layer, where less of the work function metal layer is oxidized between the first nanostructure and an adjacent second nanostructure in a stack in the fin, removing oxidized portions of the first work function metal layer from around the first nanostructure, and forming a second work function metal layer around the first nanostructure, where the first work function metal layer and the second work function metal layer fill a void between the first nanostructure and the adjacent second nanostructure.

Abstract: A method includes removing a dummy gate stack to form a trench between gate spacers, and removing a sacrificial layer contacting a semiconductor region. The sacrificial layer and the semiconductor region are in the trench. The method further includes depositing a gate dielectric into the trench and on the semiconductor region, depositing a liner on the gate dielectric, depositing a fluorine-containing layer over the liner, performing a drive-in process to drive fluorine in the fluorine-containing layer into the gate dielectric, and depositing a conductive layer over the gate dielectric.

Abstract: Disclosed is a semiconductor device and semiconductor fabrication method. A semiconductor device includes: a gate structure over a semiconductor substrate, having a high-k dielectric layer, a p-type work function layer, an n-type work function layer, a dielectric anti-reaction layer, and a glue layer; and a continuous metal cap over the gate structure formed by metal material being deposited over the gate structure, a portion of the anti-reaction layer being selectively removed, and additional metal material being deposited over the gate structure. A semiconductor fabrication method includes: receiving a gate structure; flattening the top layer of the gate structure; precleaning and pretreating the surface of the gate structure; depositing metal material over the gate structure to form a discontinuous metal cap; selectively removing a portion of the anti-reaction layer; depositing additional metal material over the gate structure to create a continuous metal cap; and containing growth of the metal cap.

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a gate structure. The gate structure includes a gate dielectric layer, an n-type work function layer embedded in the gate dielectric layer, a dielectric capping layer embedded in the n-type work function layer, and a p-type work function layer embedded in the dielectric capping layer. A top surface of the gate structure exposes the n-type work function layer, the dielectric capping layer, and the p-type work function layer. The semiconductor structure also includes a first metal cap on the n-type work function layer and a second metal cap on the p-type work function layer. The first metal cap is spaced apart from the second metal cap. without formed on the dielectric capping layer.

Abstract: Disclosed is a semiconductor device and semiconductor fabrication method. A semiconductor device includes: a gate structure over a semiconductor substrate, having a high-k dielectric layer, a p-type work function layer, an n-type work function layer, a dielectric anti-reaction layer, and a glue layer; and a continuous metal cap over the gate structure formed by metal material being deposited over the gate structure, a portion of the anti-reaction layer being selectively removed, and additional metal material being deposited over the gate structure. A semiconductor fabrication method includes: receiving a gate structure; flattening the top layer of the gate structure; precleaning and pretreating the surface of the gate structure; depositing metal material over the gate structure to form a discontinuous metal cap; selectively removing a portion of the anti-reaction layer; depositing additional metal material over the gate structure to create a continuous metal cap; and containing growth of the metal cap.

Abstract: A method according to the present disclosure includes providing a substrate that includes a dummy gate stack wrapping over an active region, and a spacer layer extending along sidewalls of the dummy gate stack, selectively removing the dummy gate stack to form a gate trench exposing the active region, depositing a gate dielectric over the active region, depositing at least one work function layer over the gate dielectric layer, depositing a tungsten layer over the at least one work function layer, and depositing a tungsten nitride layer over the tungsten layer.

Abstract: A semiconductor device includes an active region. A metal gate electrode is disposed over the active region. A conductive layer is disposed over the metal gate electrode. A silicon-containing layer is disposed over a first portion of the conductive layer. A dielectric layer is disposed over a second portion of the conductive layer. A gate via vertically extends through the silicon-containing layer. The gate via is disposed over, and electrically coupled to, the metal gate electrode.

Abstract: A method includes depositing a gate dielectric layer on a first channel region; depositing a p-type work function tuning layer on the gate dielectric layer; exposing the p-type work function tuning layer to a silicon-based precursor for a duration of time; and depositing a n-type work function tuning layer on the p-type work function tuning layer. Exposing the p-type work function tuning layer to the silicon-based precursor can form a silicon-containing layer on the p-type work function tuning layer.

Abstract: A method for determining immune competence against severe acute respiratory syndrome coronavirus 2 (SARS-CoV-2) includes obtaining a blood sample from a subject in need thereof, detecting, in the blood sample, levels of binding antibodies against SARS-CoV-2 spike S1 protein and its receptor binding domain (RBD), and calculating a weighted value using a regression model. Another method for determining immune competence against SARS-CoV-2 is also disclosed.

Abstract: A method includes depositing a gate dielectric layer on a first channel region; depositing a p-type work function tuning layer on the gate dielectric layer; exposing the p-type work function tuning layer to a silicon-based precursor for a duration of time; and depositing a n-type work function tuning layer on the p-type work function tuning layer. Exposing the p-type work function tuning layer to the silicon-based precursor can form a silicon-containing layer on the p-type work function tuning layer.

Abstract: A method includes forming a p-type transistor. The method includes forming a gate dielectric on a semiconductor region, and depositing a p-type work-function layer on the gate dielectric. The p-type work-function layer includes a metal nitride, which includes a first metal and a second metal. An n-type work-function layer is deposited over the p-type work-function layer. A p-type source/drain region is formed aside of the semiconductor region.

Abstract: An IC (integrated circuit) package includes a first interconnect. The first interconnect includes a first surface having connection pads. The connection pads include pillars extending in a direction normal to the first surface and a second surface opposing the first surface having connection pads for leads. The IC package also includes a second interconnect including the leads mounted on the connection pads of the second surface of the first interconnect and a die mounted with solder bumps on the connection pads of the first surface of the first interconnect. A portion of the solder bumps flow over the pillars.

Abstract: An example microelectronic device package includes an integrated system device, further including: at least two semiconductor dies embedded in dielectric material and spaced from one another; layers of trace level conductors formed over the at least two semiconductor dies, and layers of connection level conductors extending through layers of dielectric material between the layers of trace level conductors, the integrated system device having conductive lands on a board side surface exposed from dielectric material. A package substrate has a first set of conductive leads on one side spaced from a second set of conductive leads on an opposite side. The conductive lands are mounted to internal ends of the first set of conductive leads and to internal ends of the second set of conductive leads. Mold compound covers the integrated system device, portions of the first set of leads, and portions of the second set of leads.

Abstract: An IC (integrated circuit) package includes a first interconnect. The first interconnect includes a first surface comprising connection pads. The connection pads include cavity pillars on the first surface and the cavity pillars include a recess in the first surface with a pillar in a center region of a respective cavity pillar. The first interconnect includes a second surface opposing the first surface having connection pads for leads. The IC package includes a second interconnect with the leads mounted on the connection pads of the second surface of the first interconnect. The IC package also includes a die mounted with solder bumps on the connection pads of the first surface of the first interconnect. A portion of the solder bumps flow over the cavity pillars.

Abstract: A method includes forming a p-type transistor. The method includes forming a gate dielectric on a semiconductor region, and depositing a p-type work-function layer on the gate dielectric. The p-type work-function layer includes a metal nitride, which includes a first metal and a second metal. An n-type work-function layer is deposited over the p-type work-function layer. A p-type source/drain region is formed aside of the semiconductor region.