Abstract: A method for fabricating a load on a substrate is disclosed. The method includes the steps of: forming a dielectric layer over the substrate; patterning the dielectric layer to form a window in which a portion of the substrate is exposed; forming a metal plug in the window; forming a conducting layer over the substrate; thermally processing the metal plug and the conducting layer, thereby forming a silicide interface; and defining a predetermined length of the conducting layer from the silicide interface as a load.

Abstract: A method of forming local interconnection of a SRAM, including the following steps: First, an NMOS and a PMOS are formed on a P-well and an N-well on a substrate, respectively. An isolation oxide layer is formed and the isolation oxide layer on a node is removed. A thin polysilicon layer is formed and N+ shallow implantation and N+ deep implantation is performed by using a photolithography technique. Also, P+ shallow implantation and P+ deep implantation are performed by using a photolithography technique. After the formation of a low resistance material, the low resistance material and the thin polysilicon layer are together formed.

Abstract: A self-aligned suicide SRAM load structure and its manufacturing method comprising the steps of providing a semiconductor substrate; then forming a first insulating layer over the substrate and etching an opening. Thereafter, a polysilicon layer is formed over the first insulating layer and the opening, and then a second insulating layer is formed over the polysilicon layer. Next, a photoresist layer for creating a connector pattern is formed over the second insulating layer using microlithographic processes. The second insulating layer is then etched to expose portions of the polysilicon layer. Subsequently, a metallic layer is deposited over the exposed polysilicon layer and the second insulating layer. Then, the metallic layer reacts with the polysilicon layer through heating until the two layers are completely converted into a metal silicide layer. The metal silicide layer functions as connectors, and the unreacted polysilicon layer beneath the second insulating layer functions as a polysilicon load.

Abstract: The invention relates to a method of forming trenches having different depths in a substrate of an IC using different refractory metal layers. The depths of the trenches can be changed by controlling the thicknesses of the refractory metal layers. The profiles of the trenches can be also changed by controlling operating parameters, such as temperature, reaction time, and so on. Thus, trenches having different depths are generated.

Abstract: A memory cell manufacturing method includes the steps of: providing a silicon substrate with buried regions that are spaced by a channel; depositing a gate oxide layer over the substrate; removing a portion of the gate oxide layer which is over the channel; depositing a first polysilicon layer over remaining portions of the gate oxide layer and over exposed portion of the substrate; growing an insulating layer over the polysilicon layer; providing a first mask on the insulating layer, the mask having a length shorter than that of the insulating layer and two end portions which overlap respectively the buried regions; etching portions of the insulating layer and the polysilicon layer not covered by the mask; depositing a thin oxide layer over a remaining portion of the insulating layer; depositing a second polysilicon layer over the thin oxide layer and over the buried layers; providing a second mask, which has a width narrower than that of the second polysilicon layer, on the second polysilicon layer to defin