Patents by Inventor Kuei Chen Liang
Kuei Chen Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8916980Abstract: An apparatus includes an image sensor with a frontside and a backside. The image sensor includes an active circuit region and bonding pads. The active circuit region has a first shape that is substantially rectangular. The substantially rectangular first shape has first chamfered corners. A perimeter of the frontside of the image sensor has a second shape that is substantially rectangular. The second substantially rectangular shape has second chamfered corners. The bonding pads are disposed on the frontside of the image sensor. The bonding pads are disposed between the first chamfered corners and the second chamfered corners. The first shape is disposed inside the second shape.Type: GrantFiled: February 16, 2012Date of Patent: December 23, 2014Assignee: OmniVision Technologies, Inc.Inventors: Tiejun Dai, Kuei Chen Liang
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Publication number: 20130214375Abstract: An apparatus includes an image sensor with a frontside and a backside. The image sensor includes an active circuit region and bonding pads. The active circuit region has a first shape that is substantially rectangular. The substantially rectangular first shape has first chamfered corners. A perimeter of the frontside of the image sensor has a second shape that is substantially rectangular. The second substantially rectangular shape has second chamfered corners. The bonding pads are disposed on the frontside of the image sensor. The bonding pads are disposed between the first chamfered corners and the second chamfered corners. The first shape is disposed inside the second shape.Type: ApplicationFiled: February 16, 2012Publication date: August 22, 2013Applicant: OMNIVISION TECHNOLOGIES, INC.Inventors: Tiejun Dai, Kuei Chen Liang
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Publication number: 20060226534Abstract: A packaging structure and an assembly method are disclosed. A packaging structure includes a substrate, a die, conductive wires, and conductively filled material. The substrate includes a conductive structure, and the conductive wires are insulator-coated. The die is mounted on the substrate, and the conductive wires are connected between the die and the conductive structure. The conductively filled material is formed among the conductive wires. In the assembly method, the die is firstly mounted on the substrate, followed by connecting the conductive wires between the die and the conductive structure, and finally forming the conductively filled material among the conductive wires.Type: ApplicationFiled: March 20, 2006Publication date: October 12, 2006Applicant: Silicon Integrated Systems Corp.Inventors: Kuei-Chen Liang, Chung-Ju Wu, Chung-Yin Fang
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Patent number: 6933600Abstract: The invention provides a semiconductor package substrate, which includes a substrate, a chip contact area, an inner pad portion, an outer pad portion and a conductive layer. The chip contact area, the inner pad portion, the outer pad portion and the conductive layer are formed on one side of the substrate, wherein the outer pad portion encloses the inner pad portion that surrounds the chip contact area in the center of the substrate. The inner pad portion and the outer pad portion contain a plurality of signal pads and a plurality of shielding pads respectively, while the conductive layer and each of the shielding pads are electrically connected.Type: GrantFiled: May 20, 2002Date of Patent: August 23, 2005Assignee: Silicon Integrated Systems Corp.Inventors: Chung Ju Wu, Kuei Chen Liang, Wei Feng Lin
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Patent number: 6765301Abstract: An integrated circuit device. The substrate includes a signal connection point and two shielding connection points set at the two sides of the signal connection point. The chip is set on the substrate. There are a signal pad and two shielding pads set at the two sides of the signal pad on the edge of the chip. The signal wire bonding is coupled to the signal connection point and the signal pad. Two shielding wire bondings are coupled to the shielding connection points and the shielding pads and extend along both sides of the signal wire bonding. The signal trace line is set on the substrate and coupled to the signal connection point. The power ring circuit is set on the substrate and coupled to the shielding connection points. The power circuit includes two shielding lines extending along both sides of the signal trace line.Type: GrantFiled: August 6, 2002Date of Patent: July 20, 2004Assignee: Silicon Integrated Systems Corp.Inventors: Chung-Ju Wu, Kuei-Chen Liang, Wei-Feng Lin
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Patent number: 6744128Abstract: An integrated circuit package capable of improving signal quality is disclosed. The integrated circuit package comprises a first substrate, an integrated circuit chip attached on the first surface of the first substrate. This integrated circuit package further comprises a plurality of external terminals mounted on the first substrate and a plurality of first bonding pads mounted on the edge portion of the first surface of the first substrate and respectively connected to the corresponding external terminals. Also, the integrated circuit package further comprises a second substrate and a plurality of second bonding pads mounted on the second surface of the second substrate and connected to the first bonding pads formed on the first substrate. Furthermore, this integrated circuit package further comprises a plurality of passive components disposed on the second substrate.Type: GrantFiled: October 3, 2002Date of Patent: June 1, 2004Assignee: Silicon Integrated Systems Corp.Inventors: Chung-Ju Wu, Kuei-Chen Liang, Wei-Feng Lin
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Publication number: 20030160294Abstract: The invention provides a semiconductor package substrate, which includes a substrate, a chip contact area, an inner pad portion, an outer pad portion and a conductive layer. The chip contact area, the inner pad portion, the outer pad portion and the conductive layer are formed on one side of the substrate, wherein the outer pad portion encloses the inner pad portion that surrounds the chip contact area in the center of the substrate. The inner pad portion and the outer pad portion contain a plurality of signal pads and a plurality of shielding pads respectively, while the conducti0ve layer and each of the shielding pads are electrically connected.Type: ApplicationFiled: May 20, 2002Publication date: August 28, 2003Inventors: Chung Ju Wu, Kuei Chen Liang, Wei Feng Lin
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Publication number: 20030122238Abstract: An integrated circuit package capable of improving signal quality is disclosed. The integrated circuit package comprises a first substrate, an integrated circuit chip attached on the first surface of the first substrate. This integrated circuit package further comprises a plurality of external terminals mounted on the first substrate and a plurality of first bonding pads mounted on the edge portion of the first surface of the first substrate and respectively connected to the corresponding external terminals. Also, the integrated circuit package further comprises a second substrate and a plurality of second bonding pads mounted on the second surface of the second substrate and connected to the first bonding pads formed on the first substrate. Furthermore, this integrated circuit package further comprises a plurality of passive components disposed on the second substrate.Type: ApplicationFiled: October 3, 2002Publication date: July 3, 2003Inventors: Chung-Ju Wu, Kuei-Chen Liang, Wei-Feng Lin
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Publication number: 20030094703Abstract: An integrated circuit device. The substrate includes a signal connection point and two shielding connection points set at the two sides of the signal connection point. The chip is set on the substrate. There are a signal pad and two shielding pads set at the two sides of the signal pad on the edge of the chip. The signal wire bonding is coupled to the signal connection point and the signal pad. Two shielding wire bondings are coupled to the shielding connection points and the shielding pads and extend along both sides of the signal wire bonding. The signal trace line is set on the substrate and coupled to the signal connection point. The power ring circuit is set on the substrate and coupled to the shielding connection points. The power circuit includes two shielding lines extending along both sides of the signal trace line.Type: ApplicationFiled: August 6, 2002Publication date: May 22, 2003Inventors: Chung-Ju Wu, Kuei-Chen Liang, Wei-Feng Lin
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Publication number: 20030067048Abstract: An integrated circuit device. The integrated circuit device comprises a chip having a plurality of ground pads and power pads, a substrate having a ground ring and a power ring, and a plurality of first and second bonding wires electrically connecting the ground and power pads to the ground and power ring, wherein the ground pads are arranged closely in a first group and the power pads are arranged closely in a second group, thereby separating the first and second bonding wires from each other.Type: ApplicationFiled: August 6, 2002Publication date: April 10, 2003Inventors: Wei-Feng Lin, Chung-Ju Wu, Kuei-Chen Liang