Patents by Inventor Kuei-Chun Hung
Kuei-Chun Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240151752Abstract: An apparatus and a method for analyzing an electrical load include: receiving household electricity consumption data and household characteristic data of a user from a client device; selecting an electricity consumption analysis model according to household environment data of the user, and generating an electricity consumption tracking list according to a plurality of feature data of the household electricity consumption data and the household characteristic data via the electricity consumption analysis model; and transmitting the electricity consumption tracking list to the client device. An apparatus for modeling an electrical load includes: receiving a plurality of household electricity consumption data and of household characteristic data from client devices; and generating a plurality of electricity consumption analysis models according to the plurality of household electricity consumption data and the plurality of household characteristic data of the plurality of users.Type: ApplicationFiled: November 18, 2022Publication date: May 9, 2024Inventors: Kuang Ping Tseng, Yung Chieh Hung, Kuei Chun Chiang, Wen Jen Ho
-
Publication number: 20240085466Abstract: A power consumption behavior analyzing device and a power consumption behavior analyzing method are provided.Type: ApplicationFiled: October 25, 2022Publication date: March 14, 2024Inventors: SU-AN LIU, KUEI-CHUN CHIANG, YUNG-CHIEH HUNG
-
Publication number: 20240085465Abstract: A method and a system for identifying an operating status of an electrical appliance based on non-intrusive load monitoring are provided. The method includes the following steps. Total power consumption history data of a target field and appliance power consumption history data of target electrical appliances are obtained. The appliance power consumption history data of each target electrical appliance is converted into a binary data set. The total power consumption history data is clustered into cluster samples to obtain first feature data sets, which are then dimensionally reduced into second feature data sets, and a machine learning model is trained by using the second feature data sets and the binary data sets of the target electrical appliances to establish an operation identification model for the target electrical appliances. The operation identification model identifies an operating status of the target electrical appliances according to total power consumption data.Type: ApplicationFiled: October 26, 2022Publication date: March 14, 2024Inventors: KUANG-PING TSENG, WEN-JEN HO, YUNG-CHIEH HUNG, KUEI-CHUN CHIANG
-
Patent number: 11482517Abstract: An integrated circuit process includes the following steps. A substrate including a first area and a second area is provided. A plurality of line patterns cover the substrate of the first area, and a sacrificial line pattern covers the substrate of the second area, wherein these line patterns separate from and are orthogonal to the sacrificial line pattern. The present invention also provides an integrated circuit formed by said process. A substrate includes a first area and a second area; a plurality of line patterns cover the substrate of the first area; a slot pattern is in the substrate of the second area, wherein these line patterns are orthogonal to the slot pattern. Additionally, a plurality of line patterns cover the substrate; a sacrificial line pattern is at ends of the line patterns, wherein these line patterns separate from and are orthogonal to the sacrificial line pattern.Type: GrantFiled: May 16, 2018Date of Patent: October 25, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: En-Chiuan Liou, Chih-Wei Yang, Kuei-Chun Hung
-
Publication number: 20180261589Abstract: An integrated circuit process includes the following steps. A substrate including a first area and a second area is provided. A plurality of line patterns cover the substrate of the first area, and a sacrificial line pattern covers the substrate of the second area, wherein these line patterns separate from and are orthogonal to the sacrificial line pattern. The present invention also provides an integrated circuit formed by said process. A substrate includes a first area and a second area; a plurality of line patterns cover the substrate of the first area; a slot pattern is in the substrate of the second area, wherein these line patterns are orthogonal to the slot pattern. Additionally, a plurality of line patterns cover the substrate; a sacrificial line pattern is at ends of the line patterns, wherein these line patterns separate from and are orthogonal to the sacrificial line pattern.Type: ApplicationFiled: May 16, 2018Publication date: September 13, 2018Inventors: En-Chiuan Liou, Chih-Wei Yang, Kuei-Chun Hung
-
Patent number: 9905562Abstract: A semiconductor IC layout structure includes a plurality of first active regions arranged along a second direction, a plurality of second active regions arranged along the second direction, a plurality of gate structures extending along a first direction and respectively straddling the first active regions and the second active regions, a plurality of first conductive structures extending along the first direction, and a plurality of second conductive structures formed on the gate structures. The second active regions are isolated from the first active regions. The first direction is perpendicular to the second direction. The first conductive structures are formed on the first active regions and the second active regions. The second conductive structures include a plurality of slot-type second conductive structures extended along the second direction and a plurality of island-type second conductive structures formed on the gate structures.Type: GrantFiled: April 10, 2017Date of Patent: February 27, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shih-Chin Lin, Kuei-Chun Hung, Jerry Che Jen Hu, Ming-Jui Chen, Chen-Hsien Hsu
-
Publication number: 20170221897Abstract: A semiconductor IC layout structure includes a plurality of first active regions arranged along a second direction, a plurality of second active regions arranged along the second direction, a plurality of gate structures extending along a first direction and respectively straddling the first active regions and the second active regions, a plurality of first conductive structures extending along the first direction, and a plurality of second conductive structures formed on the gate structures. The second active regions are isolated from the first active regions. The first direction is perpendicular to the second direction. The first conductive structures are formed on the first active regions and the second active regions. The second conductive structures include a plurality of slot-type second conductive structures extended along the second direction and a plurality of island-type second conductive structures formed on the gate structures.Type: ApplicationFiled: April 10, 2017Publication date: August 3, 2017Inventors: Shih-Chin Lin, Kuei-Chun Hung, Jerry CHE JEN HU, Ming-Jui Chen, Chen-Hsien Hsu
-
Patent number: 9673145Abstract: A semiconductor integrated circuit layout structure includes a first active region, a second active region isolating from the first active region, a gate structure straddling the first active region and the second active region, and a plurality of conductive structures. The first active region at two opposite sides of the gate structure respectively forms a first source region and a first drain region. The second active region at two opposite sides of the gate structure respectively forms a second source region and a second drain region. The conductive structures include a plurality of slot-type conductive structures and one island-type conductive structure. The slot-type conductive structures are respectively formed on the first source region, the first drain region, the second source region and the second drain region. The island-type conductive structure is formed on the gate structure.Type: GrantFiled: September 21, 2015Date of Patent: June 6, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shih-Chin Lin, Kuei-Chun Hung, Jerry Che Jen Hu, Ming-Jui Chen, Chen-Hsien Hsu
-
Patent number: 9653346Abstract: An integrated circuits structure includes a semiconductor substrate, at least an non-planar field effect transistor (FET) device formed on the semiconductor substrate, and an interconnection structure formed on the semiconductor substrate. The non-planar FET device includes a plurality of fins and a gate electrode. The interconnection structure includes a plurality of first group metals and a plurality of second group metals. The first group metals are formed on the non-planar FET and the second group metals are formed on the first group metals. The first group metals include a first metal pitch and the second group metals include a second metal pitch. The second metal pitch is 1.2-1.5 times to the first metal pitch.Type: GrantFiled: July 16, 2015Date of Patent: May 16, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shih-Chin Lin, Kuei-Chun Hung, Jerry Che Jen Hu, Ming-Jui Chen, Chen-Hsien Hsu
-
Publication number: 20170117151Abstract: An integrated circuit process includes the following steps. A substrate including a first area and a second area is provided. A plurality of line patterns cover the substrate of the first area, and a sacrificial line pattern covers the substrate of the second area, wherein these line patterns separate from and are orthogonal to the sacrificial line pattern. The present invention also provides an integrated circuit formed by said process. A substrate includes a first area and a second area; a plurality of line patterns cover the substrate of the first area; a slot pattern is in the substrate of the second area, wherein these line patterns are orthogonal to the slot pattern. Additionally, a plurality of line patterns cover the substrate; a sacrificial line pattern is at ends of the line patterns, wherein these line patterns separate from and are orthogonal to the sacrificial line pattern.Type: ApplicationFiled: November 19, 2015Publication date: April 27, 2017Inventors: En-Chiuan Liou, Chih-Wei Yang, Kuei-Chun Hung
-
Patent number: 9524362Abstract: A method of decomposing pattern layout for generating patterns on photomasks is disclosed. The method includes decomposing features of an integrated circuit layout into discrete patterns based on the relation between these features. The features include first features and second features. The first features are then classified into a first feature pattern and a second feature pattern, and the second features are classified into third, fourth, fifth and sixth feature patterns. The spacings of the second features in the fifth and sixth feature patterns are greater than a minimum exposure limits. Finally, the first feature pattern is outputted to a first photomask, the second feature pattern is outputted to a second photomask, the third and fifth feature patterns are outputted to a third photomask, and the fourth and sixth feature patterns are outputted to a fourth photomask.Type: GrantFiled: April 21, 2015Date of Patent: December 20, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Harn-Jiunn Wang, Kuei-Chun Hung, Chih-Hsien Tang, Chin-Lung Lin
-
Publication number: 20160329276Abstract: A semiconductor integrated circuit layout structure includes a first active region, a second active region isolating from the first active region, a gate structure straddling the first active region and the second active region, and a plurality of conductive structures. The first active region at two opposite sides of the gate structure respectively forms a first source region and a first drain region. The second active region at two opposite sides of the gate structure respectively forms a second source region and a second drain region. The conductive structures include a plurality of slot-type conductive structures and one island-type conductive structure. The slot-type conductive structures are respectively formed on the first source region, the first drain region, the second source region and the second drain region. The island-type conductive structure is formed on the gate structure.Type: ApplicationFiled: September 21, 2015Publication date: November 10, 2016Inventors: Shih-Chin Lin, Kuei-Chun Hung, Jerry CHE JEN HU, Ming-Jui Chen, Chen-Hsien Hsu
-
Publication number: 20160329241Abstract: An integrated circuits structure includes a semiconductor substrate, at least an non-planar field effect transistor (FET) device formed on the semiconductor substrate, and an interconnection structure formed on the semiconductor substrate. The non-planar FET device includes a plurality of fins and a gate electrode. The interconnection structure includes a plurality of first group metals and a plurality of second group metals. The first group metals are formed on the non-planar FET and the second group metals are formed on the first group metals. The first group metals include a first metal pitch and the second group metals include a second metal pitch. The second metal pitch is 1.2-1.5 times to the first metal pitch.Type: ApplicationFiled: July 16, 2015Publication date: November 10, 2016Inventors: Shih-Chin LIN, Kuei-Chun HUNG, Jerry Che Jen HU, Ming-Jui CHEN, Chen-Hsien HSU
-
Publication number: 20160314233Abstract: A method of decomposing pattern layout for generating patterns on photomasks is disclosed. The method includes decomposing features of an integrated circuit layout into discrete patterns based on the relation between these features. The features include first features and second features. The first features are then classified into a first feature pattern and a second feature pattern, and the second features are classified into third, fourth, fifth and sixth feature patterns. The spacings of the second features in the fifth and sixth feature patterns are greater than a minimum exposure limits. Finally, the first feature pattern is outputted to a first photomask, the second feature pattern is outputted to a second photomask, the third and fifth feature patterns are outputted to a third photomask, and the fourth and sixth feature patterns are outputted to a fourth photomask.Type: ApplicationFiled: April 21, 2015Publication date: October 27, 2016Inventors: Harn-Jiunn Wang, Kuei-Chun Hung, Chih-Hsien Tang, Chin-Lung Lin
-
Publication number: 20150276382Abstract: A measurement mark structure includes a mark pattern and a pair of assistant bars positioned at two opposite sides of the mark pattern. The mark pattern includes a plurality of segments. The segments of the mark pattern are arranged along a first direction and the pair of the assistant bars are expend along the first direction.Type: ApplicationFiled: March 27, 2014Publication date: October 1, 2015Applicant: UNITED MICROELECTRONICS CORP.Inventors: En-Chiuan Liou, Kuei-Chun Hung, Chun-Chi Yu
-
Patent number: 9007571Abstract: A measurement method of an overlay mark is provided. An overlay mark on a wafer is measured with a plurality of different wavelength regions of an optical measurement tool, so as to obtain a plurality of overlay values corresponding to the wavelength regions. The overlay mark on the wafer is measured with an electrical measurement tool to obtain a reference overlay value. The wavelength region that corresponds to the overlay value closest to the reference overlay value is determined as a correct wavelength region for the overlay mark.Type: GrantFiled: August 20, 2013Date of Patent: April 14, 2015Assignee: United Microelectronics Corp.Inventors: Wei-Jhe Tzai, Kuei-Chun Hung, Chun-Chi Yu, Chien-Hao Chen, Chia-Ching Lin
-
Publication number: 20150055125Abstract: A measurement method of an overlay mark is provided. An overlay mark on a wafer is measured with a plurality of different wavelength regions of an optical measurement tool, so as to obtain a plurality of overlay values corresponding to the wavelength regions. The overlay mark on the wafer is measured with an electrical measurement tool to obtain a reference overlay value. The wavelength region that corresponds to the overlay value closest to the reference overlay value is determined as a correct wavelength region for the overlay mark.Type: ApplicationFiled: August 20, 2013Publication date: February 26, 2015Applicant: United Microelectronics Corp.Inventors: Wei-Jhe Tzai, Kuei-Chun Hung, Chun-Chi Yu, Chien-Hao Chen, Chia-Ching Lin
-
Patent number: 7101796Abstract: A method for forming a plane structure. It comprises the following steps: forms a liquid material with a thicker thickness on a substrate, rotating both the liquid material and the substrate around the axis of the substrate, applying a solvent on the rotating liquid material to remove partial liquid material. It also comprises the following steps: form a thicker removable material on a substrate, and partially remove the surface part of the removable material.Type: GrantFiled: April 10, 2003Date of Patent: September 5, 2006Assignee: United Microelectronics Corp.Inventors: Jui-Tsen Huang, Kuei-Chun Hung
-
Publication number: 20050277301Abstract: A method for forming a plane structure. It comprises the following steps: forms a liquid material with a thicker thickness on a substrate, rotating both the liquid material and the substrate around the axis of the substrate, applying a solvent on the rotating liquid material to remove partial liquid material. It also comprises the following steps: form a thicker removable material on a substrate, and partially remove the surface part of the removable material.Type: ApplicationFiled: August 4, 2005Publication date: December 15, 2005Applicant: UNITED MICROELECTRONICS CORP.Inventors: Jui-Tsen Huang, Kuei-Chun Hung
-
Patent number: 6839126Abstract: A photolithography process with multiple exposures is provided. A photomask is placed and aligned above a wafer having a photoresist formed thereon at a predetermined distance. Multiple exposures are sequentially performed on the photoresist through the photomask. Each of the multiple exposures is provided with a respective illuminating setting that is optimized for one duty ratio of the photomask. Thereby, an optimum through-pitch performance for pattern transfer from the photomask unto the photoresist is obtained. Then, a development is performed on the photoresist.Type: GrantFiled: January 3, 2002Date of Patent: January 4, 2005Assignee: United Microelectronics Corp.Inventors: Yeong-Song Yen, I-Hsiung Huang, Jiunn-Ren Hwang, Kuei-Chun Hung, Ching-Hsu Chang