Abstract: A video conference device may include at least one camera, at least one processor, and an interface. The at least one camera may be arranged to capture an image of a scene. The at least one processor may be arranged to: if a trigger occurs, detect a display region in the image based on a location of a pattern in the image, wherein in response to the display region being detected, the display region is excluded from the image; detect at least one specific object in the image; and extract the at least one detected specific object in the image as at least one local image. The interface may be arranged to transmit the at least one local image.

Abstract: The present invention is directed to a system and method of adaptively controlling a light-emitting diode (LED) backlight. A content analyzer analyzes luminance of image data to be displayed on a display panel. An LED current controller controls illumination of the LED backlight via an LED driver according to an analysis result of the content analyzer. The LED current controller over-drives the LED backlight such that a drive current flowing in the LED backlight is above a normal current, when the analysis result of the content analyzer indicates that the luminance of image data is above a predetermined value.

Abstract: An image enhancement apparatus is provided. The image enhancement apparatus includes a global tone mapping curve generator, a local tone mapping curve generator, a reference gamma voltage generator and an image generator. The global tone mapping curve generator generates a global tone mapping curve for an input image according to global characteristic(s) of the input image. The local tone mapping curve generator generates a local tone mapping curve for each image partition within the input image according to the global tone mapping curve and further a feature of the image partition. The reference gamma voltage generator generates a plurality of reference gamma voltages for each image partition according to the corresponding local tone mapping curve for the image partition. The image generator generates an output image according to the reference gamma voltages of the image partitions and the input image.

Abstract: An image processing module with less line buffers is provided. The image processing module receives an original image signal to drive a display panel. The image processing module includes a timing controller and a scaler. The timing controller includes a line buffer and a control unit. The line buffer registers the original image signal and outputs a storage image signal. The scaler receives the storage image signal, adjusts the resolution of the storage image signal, and outputs a scaled image signal to the control unit according to the resolution of the storage image signal. The control unit receives the scaled image signal and outputs a display signal to drive the display panel according to the scaled image signal.

Abstract: An image enhancement apparatus is provided. The image enhancement apparatus includes a global tone mapping curve generator, a local tone mapping curve generator, a reference gamma voltage generator and an image generator. The global tone mapping curve generator generates a global tone mapping curve for an input image according to global characteristic(s) of the input image. The local tone mapping curve generator generates a local tone mapping curve for each image partition within the input image according to the global tone mapping curve and further a feature of the image partition. The reference gamma voltage generator generates a plurality of reference gamma voltages for each image partition according to the corresponding local tone mapping curve for the image partition. The image generator generates an output image according to the reference gamma voltages of the image partitions and the input image.

Abstract: A display device including a remote control unit and a display panel unit is provided. The display panel unit includes a plurality of optical receivers and a track recognizer. The remote control unit emits a light beam. The optical receivers receive the light beam and convert the light beam into a plurality of sensing voltages. The track recognizer generates a control command according to the sensing voltages so that the display panel unit sets an on-screen display (OSD).

Abstract: A display driving circuit including a color correction unit and a driving unit is provided. The color correction unit receives a digital video signal and a polarity signal, and outputs a color corrected video signal according to the received digital video signal and the polarity signal, wherein the polarity signal represents the polarity of the driving polarity applied on the display apparatus. The driving unit receives a color corrected video signal and accordingly has the received color corrected video signal converted into an analog driving voltage. The display apparatus displays the frame on the display panel according to the received analog driving voltage.

Abstract: A method for detecting whether or not a display mode has to be switched and for detecting a frame of a liquid crystal display panel. The frame has M vertical blocks each including K display lines each having N horizontal blocks each being composed of multiple display units. First, a horizontal block flag value of each horizontal block is obtained according to energy levels of all of the display units of the horizontal block. Then, a display line flag value of each display line is obtained according to horizontal block flag values of all of the horizontal blocks of the display line. Next, M vertical block flag values are obtained according to the display line flag values of all of the display lines in each vertical block. Then, it is determined whether or not the display mode has to be switched according to the M vertical block flag values.

Abstract: A video processing circuit with multiple-interface has a multiple-interface device, a timing controller, and a register. The timing controller is capable of sequencing and transmitting a signal of a low voltage differential signal, a reduced swing differential signal type or a transistor-transistor logic signal type to the multiple-interface device. The register sets the multiple-interface device to be adapted to output the signals of the types to a source driver.

Abstract: The present invention provides a LCOS display. The display comprises a first PCB, an interface module, a first silicon chip, and a flat cable. The interface module is disposed on the first PCB and used to receive an audio and video signal. The first silicon chip comprises a display area, a processing area, and a metal layer. The display area comprises a pixel array in a LCOS panel formed on the first silicon chip. The processing area comprises a processing unit formed on the first silicon chip. The metal layer is formed on the first silicon chip for electrically connecting the display area with the processing area. The flat cable is used to electrically connect the interface module with the processing unit.

Abstract: A control chipset for a video display apparatus is provided. The control chipset is coupled to a frame buffer and a display unit. The control chipset comprises: a scaler for receiving and processing an input video signal to generate a scaled video signal; a three-dimensional (3D) video enhancing unit for receiving and processing the scaled video signal to generate an enhanced video signal; an overdrive unit for receiving and processing the enhanced video signal to generate an overdriven video signal; a timing controller for generating a timing control signal, receiving the overdriven video signal, and transferring the timing control signal and the overdriven video signal to the display unit; and a memory controller. The scaler, the 3D video enhancing unit, and the overdriven unit access the frame buffer through the same memory controller, and data accessed by the overdrive unit is compressed.

Abstract: A method for video processing which provides a scaled image using two different clock frequencies is provided. The method receives source pixel data using a first clock signal and scales the source pixel data to destination pixel data. After that, the destination pixel data is provided using a second clock signal having a second clock frequency and a third clock signal having a third clock frequency during blanking period and active period, respectively.

Abstract: A method for accessing a single port memory is provided. A single port memory is used as a line buffer and divided into a plurality of memory blocks. The line buffer data is written into or read out from these memory blocks by turns with a special sequence corresponding to the operation mode; for example, a normal mode or a PLM mode. Therefore, the line buffer data can be written into or read out from the line buffer at the same time, and the size and cost of integrated circuit can be reduced.

Abstract: A method for video processing which provides a scaled image using two different clock frequencies is provided. The method receives source pixel data using a first clock signal and scales the source pixel data to destination pixel data. After that, the destination pixel data is provided using a second clock signal having a second clock frequency and a third clock signal having a third clock frequency during blanking period and active period, respectively.

Abstract: An image processing module with less line buffers is provided. The image processing module receives an original image signal to drive a display panel. The image processing module includes a timing controller and a scaler. The timing controller includes a line buffer and a control unit. The line buffer registers the original image signal and outputs a storage image signal. The scaler receives the storage image signal, adjusts the resolution of the storage image signal, and outputs a scaled image signal to the control unit according to the resolution of the storage image signal. The control unit receives the scaled image signal and outputs a display signal to drive the display panel according to the scaled image signal.

Abstract: A method for accessing a single port memory is provided. A single port memory is used as a line buffer and divided into a plurality of memory blocks. The line buffer data is written into or read out from these memory blocks by turns with a special sequence corresponding to the operation mode; for example, a normal mode or a PLM mode. Therefore, the line buffer data can be written into or read out from the line buffer at the same time, and the size and cost of integrated circuit can be reduced.

Abstract: A display driving circuit including a color correction unit and a driving unit is provided. The color correction unit receives a digital video signal and a polarity signal, and outputs a color corrected video signal according to the received digital video signal and the polarity signal, wherein the polarity signal represents the polarity of the driving polarity applied on the display apparatus. The driving unit receives a color corrected video signal and accordingly has the received color corrected video signal converted into an analog driving voltage. The display apparatus displays the frame on the display panel according to the received analog driving voltage.

Abstract: A method for detecting whether or not a display mode has to be switched and for detecting a frame of a liquid crystal display panel. The frame has M vertical blocks each including K display lines each having N horizontal blocks each being composed of multiple display units. First, a horizontal block flag value of each horizontal block is obtained according to energy levels of all of the display units of the horizontal block. Then, a display line flag value of each display line is obtained according to horizontal block flag values of all of the horizontal blocks of the display line. Next, M vertical block flag values are obtained according to the display line flag values of all of the display lines in each vertical block. Then, it is determined whether or not the display mode has to be switched according to the M vertical block flag values.

Abstract: The present invention provides an image data processing system to increase the speed of on-screen display (OSD) image processing. The image data processing system comprises M color code registers for storing a plurality of color codes and a first multiplexer electrically connected to every output port of the M color code registers. The first multiplexer comprises a control port for inputting an N-bit image code, and the first multiplexer chooses one of the outputs of the M color code registers as its output according to the N-bit image code. The image data processing system comprises a processor for storing M color codes in the M color code registers and periodically transmitting a plurality of N-bit image codes to the control port of the first multiplexer so that the first multiplexer periodically chooses one of the color codes stored in the M color code registers as its output according to one of the N-bit image codes.

Abstract: The present invention provides an image data processing system to increase the speed of on-screen display (OSD) image processing. The image data processing system comprises M color code registers for storing a plurality of color codes and a first multiplexer electrically connected to every output port of the M color code registers. The first multiplexer comprises a control port for inputting an N-bit image code, and the first multiplexer chooses one of the outputs of the M color code registers as its output according to the N-bit image code. The image data processing system comprises a processor for storing M color codes in the M color code registers and periodically transmitting a plurality of N-bit image codes to the control port of the first multiplexer so that the first multiplexer periodically chooses one of the color codes stored in the M color code registers as its output according to one of the N-bit image codes.