Patents by Inventor Kuei-Ming CHANG
Kuei-Ming CHANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11923253Abstract: A device includes a first transistor, a second transistor, and a dielectric structure. The first transistor is over a substrate and has a first gate structure. The second transistor is over the substrate and has a second gate structure. The dielectric structure is between the first gate structure and the second gate structure. The dielectric structure has a width increasing from a bottom position of the dielectric structure to a first position higher than the bottom position of the dielectric structure. A width of the first gate structure is less than the width of the dielectric structure at the first position.Type: GrantFiled: February 10, 2023Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuei-Ming Chang, Rei-Jay Hsieh, Cheng-Han Wu, Chie-luan Lin
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Publication number: 20230187283Abstract: A device includes a first transistor, a second transistor, and a dielectric structure. The first transistor is over a substrate and has a first gate structure. The second transistor is over the substrate and has a second gate structure. The dielectric structure is between the first gate structure and the second gate structure. The dielectric structure has a width increasing from a bottom position of the dielectric structure to a first position higher than the bottom position of the dielectric structure. A width of the first gate structure is less than the width of the dielectric structure at the first position.Type: ApplicationFiled: February 10, 2023Publication date: June 15, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuei-Ming CHANG, Rei-Jay HSIEH, Cheng-Han WU, Chie-Iuan LIN
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Patent number: 11581227Abstract: An IC structure includes a semiconductor fin, first and second gate structures, and an isolation structure. The semiconductor fin extends from a substrate. The first gate structure extends above a top surface of the semiconductor fin by a first gate height. The second gate structure is over the semiconductor fin. The isolation structure is between the first and second gate structures, and has a lower dielectric portion embedded in the semiconductor fin and an upper dielectric portion extending above the top surface of the semiconductor fin by a height that is the same as the first gate height. When viewed in a cross section taken along a longitudinal direction of the semiconductor fin, the upper dielectric portion of the isolation structure has a rectangular profile with a width greater than a bottom width of the lower dielectric portion of the isolation structure.Type: GrantFiled: July 26, 2021Date of Patent: February 14, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuei-Ming Chang, Rei-Jay Hsieh, Cheng-Han Wu, Chie-Iuan Lin
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Publication number: 20220320086Abstract: A method includes forming a semiconductor fin over a substrate; forming first, second, and third gate structures crossing the semiconductor fin; forming first source/drain epitaxy structures over the semiconductor fin and on opposite sides of the first gate structure and forming second source/drain epitaxy structures over the semiconductor fin and on opposite sides of the second gate structure, wherein bottom of the first source/drain epitaxy structures and bottom of the second source/drain epitaxy structures are lower than a top surface of the semiconductor fin; removing the third gate structure to expose the top surface of the semiconductor fin; forming an isolation structure in the semiconductor fin, wherein a bottom of the isolation structure is lower than the bottom of the first source/drain epitaxy structures and the bottom the second source/drain epitaxy structures.Type: ApplicationFiled: June 24, 2022Publication date: October 6, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Han WU, Chie-Iuan LIN, Kuei-Ming CHANG, Rei-Jay HSIEH
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Patent number: 11387232Abstract: A semiconductor device includes a substrate; a first gate stack disposed on the substrate; a second gate stack disposed on the substrate, wherein a metal component of the first gate stack is different from a metal component of the second gate stack; and a dielectric structure disposed over the substrate and between the first gate stack and the second gate stack, in which the dielectric structure is separated from the first gate stack and the second gate stack, and a distance between the dielectric structure and the first gate stack is substantially equal to a distance between the dielectric structure and the second gate stack.Type: GrantFiled: June 21, 2017Date of Patent: July 12, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Han Wu, Chie-Iuan Lin, Kuei-Ming Chang, Rei-Jay Hsieh
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Patent number: 11245034Abstract: A semiconductor device includes a substrate, first and second source/drain features, and a dielectric plug. The substrate has a semiconductor fin. The first and second source/drain features are over first and second portions of the semiconductor fin, respectively. The dielectric plug is at least partially embedded in a third portion of the semiconductor fin. The third portion is in between the first and second portions of the semiconductor fin. The dielectric plug includes a first dielectric material and a second dielectric material different from the first dielectric material.Type: GrantFiled: April 25, 2018Date of Patent: February 8, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuei-Ming Chang, Ta-Chun Lin, Rei-Jay Hsieh, Yung-Chih Wang, Wen-Huei Guo, Kuo-Hua Pan, Buo-Chin Hsu
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Publication number: 20210351086Abstract: An IC structure includes a semiconductor fin, first and second gate structures, and an isolation structure. The semiconductor fin extends from a substrate. The first gate structure extends above a top surface of the semiconductor fin by a first gate height. The second gate structure is over the semiconductor fin. The isolation structure is between the first and second gate structures, and has a lower dielectric portion embedded in the semiconductor fin and an upper dielectric portion extending above the top surface of the semiconductor fin by a height that is the same as the first gate height. When viewed in a cross section taken along a longitudinal direction of the semiconductor fin, the upper dielectric portion of the isolation structure has a rectangular profile with a width greater than a bottom width of the lower dielectric portion of the isolation structure.Type: ApplicationFiled: July 26, 2021Publication date: November 11, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuei-Ming CHANG, Rei-Jay HSIEH, Cheng-Han WU, Chie-Iuan LIN
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Patent number: 11075125Abstract: A device includes a semiconductor fin, a first transistor, a second transistor and a dielectric structure. The first semiconductor fin extends from a substrate. The first transistor is formed on a first region of the semiconductor fin. The second transistor is formed on a second region of the semiconductor fin laterally spaced apart from the first region of the semiconductor fin. The dielectric structure has a lower portion extending in the semiconductor fin and between the first transistor and the second transistor. The lower portion of the dielectric structure has a width increasing from a bottommost position of the dielectric structure to a first position higher than the bottommost position of the dielectric structure and decreasing from the first position to a second position higher than the first position.Type: GrantFiled: July 20, 2020Date of Patent: July 27, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuei-Ming Chang, Rei-Jay Hsieh, Cheng-Han Wu, Chie-Iuan Lin
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Patent number: 10872805Abstract: A semiconductor device includes a substrate, a shallow trench isolation (STI) structure, a first source/drain, a second source/drain, and an isolation dielectric. The substrate has a semiconductor fin. The STI structure surrounds the semiconductor fin. The first source/drain is embedded in the semiconductor fin. The second source/drain is embedded in the semiconductor fin. The isolation dielectric is between the first and second source/drains and extending into the semiconductor fin. An upper surface of the STI structure is free from coverage of the isolation dielectric.Type: GrantFiled: December 3, 2018Date of Patent: December 22, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuei-Ming Chang, Chi-Wei Wu, Yi-Chieh Hsieh
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Publication number: 20200350214Abstract: A device includes a semiconductor fin, a first transistor, a second transistor and a dielectric structure. The first semiconductor fin extends from a substrate. The first transistor is formed on a first region of the semiconductor fin. The second transistor is formed on a second region of the semiconductor fin laterally spaced apart from the first region of the semiconductor fin. The dielectric structure has a lower portion extending in the semiconductor fin and between the first transistor and the second transistor. The lower portion of the dielectric structure has a width increasing from a bottommost position of the dielectric structure to a first position higher than the bottommost position of the dielectric structure and decreasing from the first position to a second position higher than the first position.Type: ApplicationFiled: July 20, 2020Publication date: November 5, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuei-Ming CHANG, Rei-Jay HSIEH, Cheng-Han WU, Chie-Iuan LIN
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Patent number: 10720362Abstract: A device includes a semiconductor fin, a first source/drain feature, a second source/drain feature, and a dielectric plug. The first source/drain feature adjoins the semiconductor fin. The second source/drain feature adjoins the semiconductor fin. The dielectric plug extends from above the semiconductor fin into the semiconductor fin, the dielectric plug is between the first source/drain feature and the second source/drain feature. The dielectric plug includes a waist and a first portion below the waist, and a width of the waist is less than a width of the first portion of the dielectric plug.Type: GrantFiled: December 17, 2018Date of Patent: July 21, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuei-Ming Chang, Rei-Jay Hsieh, Cheng-Han Wu, Chie-Iuan Lin
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Publication number: 20200105581Abstract: A semiconductor device includes a substrate, a shallow trench isolation (STI) structure, a first source/drain, a second source/drain, and an isolation dielectric. The substrate has a semiconductor fin. The STI structure surrounds the semiconductor fin. The first source/drain is embedded in the semiconductor fin. The second source/drain is embedded in the semiconductor fin. The isolation dielectric is between the first and second source/drains and extending into the semiconductor fin. An upper surface of the STI structure is free from coverage of the isolation dielectric.Type: ApplicationFiled: December 3, 2018Publication date: April 2, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuei-Ming CHANG, Chi-Wei WU, Yi-Chieh HSIEH
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Publication number: 20190334035Abstract: A semiconductor device includes a substrate, first and second source/drain features, and a dielectric plug. The substrate has a semiconductor fin. The first and second source/drain features are over first and second portions of the semiconductor fin, respectively. The dielectric plug is at least partially embedded in a third portion of the semiconductor fin. The third portion is in between the first and second portions of the semiconductor fin. The dielectric plug includes a first dielectric material and a second dielectric material different from the first dielectric material.Type: ApplicationFiled: April 25, 2018Publication date: October 31, 2019Inventors: Kuei-Ming CHANG, Ta-Chun LIN, Rei-Jay HSIEH, Yung-Chih WANG, Wen-Huei GUO, Kuo-Hua PAN, Buo-Chin HSU
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Publication number: 20190122940Abstract: A device includes a semiconductor fin, a first source/drain feature, a second source/drain feature, and a dielectric plug. The first source/drain feature adjoins the semiconductor fin. The second source/drain feature adjoins the semiconductor fin. The dielectric plug extends from above the semiconductor fin into the semiconductor fin, the dielectric plug is between the first source/drain feature and the second source/drain feature. The dielectric plug includes a waist and a first portion below the waist, and a width of the waist is less than a width of the first portion of the dielectric plug.Type: ApplicationFiled: December 17, 2018Publication date: April 25, 2019Inventors: Kuei-Ming CHANG, Rei-Jay HSIEH, Cheng-Han WU, Chie-Iuan LIN
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Patent number: 10157800Abstract: A semiconductor device includes a substrate, a first source/drain feature, a second source/drain feature and a dielectric plug. The substrate has a semiconductor fin. The first source/drain feature is embedded in the semiconductor fin. The second source/drain feature is embedded in the semiconductor fin. The dielectric plug extends from above the semiconductor fin into the semiconductor fin. The dielectric plug is in between the first source/drain feature and the second source/drain feature. The dielectric plug is separated from the first source/drain feature and the second source/drain feature.Type: GrantFiled: June 28, 2017Date of Patent: December 18, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuei-Ming Chang, Rei-Jay Hsieh, Cheng-Han Wu, Chie-Iuan Lin
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Publication number: 20180308769Abstract: A semiconductor device includes a substrate, a first source/drain feature, a second source/drain feature and a dielectric plug. The substrate has a semiconductor fin. The first source/drain feature is embedded in the semiconductor fin. The second source/drain feature is embedded in the semiconductor fin. The dielectric plug extends from above the semiconductor fin into the semiconductor fin. The dielectric plug is in between the first source/drain feature and the second source/drain feature. The dielectric plug is separated from the first source/drain feature and the second source/drain feature.Type: ApplicationFiled: June 28, 2017Publication date: October 25, 2018Inventors: Kuei-Ming CHANG, Rei-Jay HSIEH, Cheng-Han WU, Chie-Iuan LIN
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Publication number: 20180277536Abstract: A semiconductor device includes a substrate; a first gate stack disposed on the substrate; a second gate stack disposed on the substrate, wherein a metal component of the first gate stack is different from a metal component of the second gate stack; and a dielectric structure disposed over the substrate and between the first gate stack and the second gate stack, in which the dielectric structure is separated from the first gate stack and the second gate stack, and a distance between the dielectric structure and the first gate stack is substantially equal to a distance between the dielectric structure and the second gate stack.Type: ApplicationFiled: June 21, 2017Publication date: September 27, 2018Inventors: Cheng-Han WU, Chie-Iuan LIN, Kuei-Ming CHANG, Rei-Jay HSIEH