Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a semiconductor device that is inverted and that overlies a dielectric region inset into a top of a semiconductor substrate. An interconnect structure overlies the semiconductor substrate and the dielectric region and further comprises an intermetal dielectric (IMD) layer. The IMD layer is bonded to the top of the semiconductor substrate and accommodates a pad. A semiconductor layer overlies the interconnect structure, and the semiconductor device is in the semiconductor layer, between the semiconductor layer and the interconnect structure. The semiconductor device comprises a first source/drain electrode overlying the dielectric region and further overlying and electrically coupled to the pad. The dielectric region reduces substrate capacitance to decrease substrate power loss and may, for example, be a cavity or a dielectric layer. A contact extends through the semiconductor layer to the pad.

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a semiconductor device that is inverted and that overlies a dielectric region inset into a top of a semiconductor substrate. An interconnect structure overlies the semiconductor substrate and the dielectric region and further comprises an intermetal dielectric (IMD) layer. The IMD layer is bonded to the top of the semiconductor substrate and accommodates a pad. A semiconductor layer overlies the interconnect structure, and the semiconductor device is in the semiconductor layer, between the semiconductor layer and the interconnect structure. The semiconductor device comprises a first source/drain electrode overlying the dielectric region and further overlying and electrically coupled to the pad. The dielectric region reduces substrate capacitance to decrease substrate power loss and may, for example, be a cavity or a dielectric layer. A contact extends through the semiconductor layer to the pad.

Abstract: A method includes forming a gate structure over a silicon on insulator (SOI) substrate. The SOI substrate comprising: a base semiconductor layer; an insulator layer over the base semiconductor layer; and a top semiconductor layer over the insulator layer. The method further includes depositing a gate spacer layer over a top surface and along a sidewall of the gate structure; etching the gate spacer layer to define a gate spacer on the sidewall of the gate structure; after etching the gate spacer layer, etching a recess into the top semiconductor layer using a first etch process; and after the first etch process, extending the recess further into the top semiconductor layer using a second etch process. The first etch process is different from the second etch process. The method further includes forming a source/drain region in the recess after the second etch process.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device including a gate electrode over a semiconductor substrate. An epitaxial source/drain layer is disposed on the semiconductor substrate and is laterally adjacent to the gate electrode. The epitaxial source/drain layer comprises a first dopant. A diffusion barrier layer is between the epitaxial source/drain layer and the semiconductor substrate. The diffusion barrier layer comprises a barrier dopant that is different from the first dopant.

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a semiconductor device that is inverted and that overlies a dielectric region inset into a top of a semiconductor substrate. An interconnect structure overlies the semiconductor substrate and the dielectric region and further comprises an intermetal dielectric (IMD) layer. The IMD layer is bonded to the top of the semiconductor substrate and accommodates a pad. A semiconductor layer overlies the interconnect structure, and the semiconductor device is in the semiconductor layer, between the semiconductor layer and the interconnect structure. The semiconductor device comprises a first source/drain electrode overlying the dielectric region and further overlying and electrically coupled to the pad. The dielectric region reduces substrate capacitance to decrease substrate power loss and may, for example, be a cavity or a dielectric layer. A contact extends through the semiconductor layer to the pad.

Abstract: Various embodiments of the present application are directed towards a group III-V device including a rough buffer layer. The rough buffer layer overlies a silicon substrate, a buffer structure overlies the rough buffer layer, and a heterojunction structure overlies the buffer structure. The buffer structure causes band bending and formation of a two-dimensional hole gas (2DHG) in the rough buffer layer. The rough buffer layer includes silicon or some other suitable semiconductor material and, in some embodiments, is doped. A top surface of the rough buffer layer and/or a bottom surface of the rough buffer layer is/are rough to promote carrier scattering along the top and bottom surfaces. The carrier scattering reduces carrier mobility and increases resistance at the 2DHG. The increased resistance increases an overall resistance of the silicon substrate, which reduces substrate loses and increases a power added efficiency (PAE).

Abstract: Various embodiments of the present application are directed towards a group III-V device including a seed buffer layer that is doped and that is directly on a silicon substrate. In some embodiments, the group III-V device includes the silicon substrate, the seed buffer layer, a heterojunction structure, a pair of source/drain electrodes, and a gate electrode. The seed buffer layer overlies and directly contacts the silicon substrate. Further, the seed buffer layer includes a group III nitride (e.g., AlN) that is doped with p-type dopants. The heterojunction structure overlies the seed buffer layer. The source/drain electrodes overlie the heterojunction structure. The gate electrode overlies the heterojunction structure, laterally between the source/drain electrodes. The p-type dopants prevent the formation of a two-dimensional hole gas (2DHG) in the silicon substrate, along an interface at which the silicon substrate and the seed buffer layer directly contact.

Abstract: The semiconductor structure includes a p-type doped III-V compound layer, a III-V compound channel layer over the p-type doped III-V compound layer, and a barrier layer. The III-V compound channel layer includes an upper region and a lower region, and the barrier layer is sandwiched between the upper region and the lower region of the III-V channel compound layer. The III-V compound channel layer includes a first band gap, the barrier layer includes a second band gap, and the second band gap is greater than the first band gap.

Abstract: An enhancement mode field-effect transistor (E-FET) for high static performance is provided. A composite barrier layer comprises a lower barrier layer and an upper barrier layer. The upper barrier layer is arranged over the lower barrier layer and has a different polarization than the lower barrier layer. Further, the composite barrier layer comprises a gate opening. A channel layer is arranged under the composite barrier layer, such that a heterojunction is defined at an interface between the channel layer and the composite barrier layer. A gate dielectric layer is arranged over the composite barrier layer and within the gate opening. A gate electrode is arranged over the gate dielectric layer. A method for manufacturing the E-FET is also provided.

Abstract: A high electron mobility transistor (HEMT) device structure is provided. The HEMT device structure includes a channel layer formed over a substrate and an active layer formed over the channel layer. The HEMT device structure also includes a gate structure formed over the active layer, and the gate structure includes: a p-doped gallium nitride (p-GaN) layer or a p-doped aluminum gallium nitride (p-GaN) layer formed over the active layer, and a portion of the p-GaN layer or p-AlGaN layer has a stepwise or gradient doping concentration. The HEMT device structure also includes a gate electrode over the p-GaN layer or p-AlGaN layer.

Abstract: A high electron mobility transistor (HEMT) device structure is provided. The HEMT device structure includes a channel layer formed over a substrate and an active layer formed over the channel layer. The HEMT device structure also includes a gate structure formed over the active layer, and the gate structure includes: a p-doped gallium nitride (p-GaN) layer or a p-doped aluminum gallium nitride (p-GaN) layer formed over the active layer, and a portion of the p-GaN layer or p-AlGaN layer has a stepwise or gradient doping concentration. The HEMT device structure also includes a gate electrode over the p-GaN layer or p-AlGaN layer.

Abstract: An enhancement mode field-effect transistor (E-FET) for high static performance is provided. A composite barrier layer comprises a lower barrier layer and an upper barrier layer. The upper barrier layer is arranged over the lower barrier layer and has a different polarization than the lower barrier layer. Further, the composite barrier layer comprises a gate opening. A channel layer is arranged under the composite barrier layer, such that a heterojunction is defined at an interface between the channel layer and the composite barrier layer. A gate dielectric layer is arranged over the composite barrier layer and within the gate opening. A gate electrode is arranged over the gate dielectric layer. A method for manufacturing the E-FET is also provided.

Abstract: A transistor with a multi-layer active layer having at least one partial recess is provided. The transistor includes a channel layer arranged over a substrate. The channel layer has a first bandgap. The transistor includes a first active layer arranged over the channel layer. The first active layer has a second bandgap different from the first band gap such that the first active layer and the channel layer meet at a heterojunction. The transistor includes a second active layer arranged over the first active layer. The transistor also includes a dielectric layer arranged over the second active layer. The transistor further includes gate electrode having gate edges that are laterally adjacent to the dielectric layer. At least one gate edge of the gate edges is laterally separated from the second active layer by a first recess.

Abstract: The invention discloses a treating method to produce various patterns on the surface by using gases with ability to etch the group III nitride semiconductor in certain conditions. The selective etching makes some specific patterns on group III nitride semiconductor surface, and different forms of the patterns can be controlled by the selective etching conditions.

Abstract: The invention discloses a smoothing method to decrease bowing of group III nitride semiconductor substrate. The certain face of group III nitride semiconductor substrates is etched under the appropriate etching recipe and time, the certain morphology such as rod-type and other structures are appeared at the certain face. And such structures releases the compressive stresses at these certain faces, resulting in clearly increasing the bowing radius of the group III nitride semiconductor substrates, finally decreasing the bowing phenomenon of the group III nitride semiconductor substrate.

Abstract: The invention discloses a smoothing method to decrease bowing of group III nitride semiconductor substrate. The certain face of group III nitride semiconductor substrates is etched under the appropriate etching recipe and time, the certain morphology such as rod-type and other structures are appeared at the certain face. And such structures releases the compressive stresses at these certain faces, resulting in clearly increasing the bowing radius of the group III nitride semiconductor substrates, finally decreasing the bowing phenomenon of the group III nitride semiconductor substrate.

Abstract: The invention discloses a treating method to produce various patterns on the surface by using gases with ability to etch the group III nitride semiconductor in certain conditions. The selective etching makes some specific patterns on group III nitride semiconductor surface, and different forms of the patterns can be controlled by the selective etching conditions.

Abstract: A method for growing a Group III-V nitride film and a structure thereof are presented. The method is carried out by hydride vapor phase epitaxy (HVPE). The method includes the steps of, inter alia, slowly epitaxially growing a temperature ramping nitride layer on a substrate by rising a first growth temperature of 900-950° C. to a second growth temperature of 1000-1050° C. at a temperature-rising rate of 0.5-10° C./min. The lattice quality of the temperature ramping nitride layer is slowly transformed with the layer height, so that a stress induced by lattice mismatch between a sapphire substrate and a gallium nitride (GaN) layer is relieved.

Abstract: A method for growing a Group III-V nitride film and a structure thereof are presented. The method is carried out by hydride vapor phase epitaxy (HVPE). The method includes the steps of, inter alia, slowly epitaxially growing a temperature ramping nitride layer on a substrate by rising a first growth temperature of 900-950° C. to a second growth temperature of 1000-1050° C. at a temperature-rising rate of 0.5-10° C./min. The lattice quality of the temperature ramping nitride layer is slowly transformed with the layer height, so that a stress induced by lattice mismatch between a sapphire substrate and a gallium nitride (GaN) layer is relieved.