Patents by Inventor Kuei Pin WAN

Kuei Pin WAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8420523
    Abstract: The present invention relates to a chip packaging method and structure, in which bonding pads provided on the chip are connected by a plurality of metal wires via bonding, each of the metal wires is bending in the middle part to be higher than a predetermined height, and its ends are respectively electrically connected with two of the bonding pads. A molding layer is packaged on the chip and the molding layer is higher than the predetermined height. The molding layer is sliced at the predetermined height. Two upper breakpoints of each metal wire are exposed and a substrate is attached onto the molding layer. A plurality of circuit contacts of the substrate are respectively electrically coupled with the upper breakpoints. Whereby, the invention is capable of reducing the length of the metal wires in order to improve transmission speed, but also to reduce the volume of the packaging structure.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: April 16, 2013
    Assignee: Kun Yuan Technology Co., Ltd.
    Inventors: Cheng-Ho Hsu, Kuei Pin Wan
  • Publication number: 20120070943
    Abstract: The present invention relates to a chip packaging method and structure, in which bonding pads provided on the chip are connected by a plurality of metal wires via bonding, each of the metal wires is bending in the middle part to be higher than a predetermined height, and its ends are respectively electrically connected with two of the bonding pads. A molding layer is packaged on the chip and the molding layer is higher than the predetermined height. The molding layer is sliced at the predetermined height. Two upper breakpoints of each metal wire are exposed and a substrate is attached onto the molding layer. A plurality of circuit contacts of the substrate are respectively electrically coupled with the upper breakpoints. Whereby, the invention is capable of reducing the length of the metal wires in order to improve transmission speed, but also to reduce the volume of the packaging structure.
    Type: Application
    Filed: November 30, 2011
    Publication date: March 22, 2012
    Applicant: Kun Yuan Technology Co., Ltd.
    Inventors: Cheng-Ho HSU, Kuei Pin Wan
  • Publication number: 20100314748
    Abstract: The present invention relates to a chip packaging method and structure, in which bonding pads provided on the chip are connected by a plurality of metal wires via bonding, each of the metal wires is bending in the middle part to be higher than a predetermined height, and its ends are respectively electrically connected with two of the bonding pads. A molding layer is packaged on the chip and the molding layer is higher than the predetermined height. The molding layer is sliced at the predetermined height. Two upper breakpoints of each metal wire are exposed and a substrate is attached onto the molding layer. A plurality of circuit contacts of the substrate are respectively electrically coupled with the upper breakpoints. Whereby, the invention is capable of reducing the length of the metal wires in order to improve transmission speed, but also to reduce the volume of the packaging structure.
    Type: Application
    Filed: September 11, 2009
    Publication date: December 16, 2010
    Applicant: Kun Yuan Technology Co., Ltd.
    Inventors: Cheng-Ho HSU, Kuei Pin WAN