Patents by Inventor Kuei Shan Wen

Kuei Shan Wen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9703917
    Abstract: Various aspects of the disclosed techniques relate to techniques for identifying high-impedance nodes in a circuit design. Noise sources are added to nodes of interest in the circuit design. Voltage values at the nodes of interest are then computed in parallel. Based on the voltage values, high impedance nodes in the nodes of interest are identified.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: July 11, 2017
    Assignee: Mentor Graphics Corporation
    Inventors: Pole Shang Lin, Kuei Shan Wen
  • Publication number: 20160210394
    Abstract: Various aspects of the disclosed techniques relate to techniques for identifying high-impedance nodes in a circuit design. Noise sources are added to nodes of interest in the circuit design. Voltage values at the nodes of interest are then computed in parallel. Based on the voltage values, high impedance nodes in the nodes of interest are identified.
    Type: Application
    Filed: January 20, 2015
    Publication date: July 21, 2016
    Inventors: Pole Shang Lin, Kuei Shan Wen
  • Patent number: 8832635
    Abstract: Aspects of the invention relate to simulation of circuits with repetitive elements. With various implementations of the invention, a circuit design for simulation is analyzed to derive information of memory-circuit device groups that comprise word-line-driven device groups. If the circuit design is hierarchically structured, the circuit design is flattened to device level but keep the memory-circuit device groups intact. The circuit design is then partitioned into a plurality of subcircuits for a simulation. During a transient simulation, whether an instance of a word-line-driven device group is activated is first determined. If activated, whether device model values exist for the word-line-driven device group at a voltage state associated with the activated instance is then determined. If they exist, the device model values are associated with the activated instance. If they do not exist, the device model values are computed for, stored for and associated with the activated instance.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: September 9, 2014
    Assignee: Mentor Graphics Corporation
    Inventors: Pole Shang Lin, Kuei Shan Wen, Ruey Kuen Perng
  • Patent number: 8352893
    Abstract: Aspects of the invention relate to circuit topology recognition and circuit partitioning. In various embodiments of the invention, diode-connected transistors can be identified in a circuit netlist based on the unique structure. From the diode-connected transistors, current mirrors can be found. The current mirrors may be employed for locating differential pairs used in the input stage of operational amplifiers and for locating supply voltage and ground nodes in the netlist. The subcircuits that are strongly connected due to feedback loops of operational amplifiers in the circuit can then be identified and grouped together for circuit analysis and simulation.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: January 8, 2013
    Assignee: Mentor Graphics Corporation
    Inventors: Pole Shang Lin, Tamer Raed Fahim Riad, Kuei Shan Wen