Patents by Inventor Kuei-Ti Chan
Kuei-Ti Chan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240079444Abstract: A semiconductor package includes a first die comprising an upper surface and a lower surface opposite to the upper surface. The first die includes a plurality of through-silicon vias (TSVs) penetrating through the first die. A second die is stacked on the upper surface of the first die. An interposer layer is disposed on the lower surface of the first die. An inductor is disposed in the interposer layer. The inductor comprises terminals directly coupled to the TSVs.Type: ApplicationFiled: June 12, 2023Publication date: March 7, 2024Applicant: MediaTek Inc.Inventors: Zheng Zeng, Ching-Chung Ko, Kuei-Ti Chan
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Patent number: 11715754Abstract: A semiconductor package includes a first die comprising an upper surface and a lower surface opposite to the upper surface. The first die includes a plurality of through-silicon vias (TSVs) penetrating through the first die. A second die is stacked on the upper surface of the first die. An interposer layer is disposed on the lower surface of the first die. An inductor is disposed in the interposer layer. The inductor comprises terminals directly coupled to the TSVs.Type: GrantFiled: May 12, 2021Date of Patent: August 1, 2023Assignee: MediaTek Inc.Inventors: Zheng Zeng, Ching-Chung Ko, Kuei-Ti Chan
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Publication number: 20220416011Abstract: Capacitor structures are provided. A capacitor structure includes a first metal line, a second metal line, a plurality of first capacitor cells coupled in parallel between the first metal line and the second metal line, and a plurality of second capacitor cells coupled in parallel between the first metal line and the second metal line. Each of the first capacitor cells includes a first bottom electrode coupled to the first metal line, a first dielectric material over the first bottom electrode, and a first top electrode over the first dielectric material and coupled to the second metal line. Each of the second capacitor cells includes a second bottom electrode coupled to the second metal line, a second dielectric material over the second bottom electrode, and a second top electrode over the second dielectric material and coupled to the first metal line.Type: ApplicationFiled: May 24, 2022Publication date: December 29, 2022Inventors: Chang LIANG, Zhigang DUAN, Kuei-Ti CHAN
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Publication number: 20220216154Abstract: A semiconductor structure includes a substrate, a first semiconductor die, a second semiconductor die, and a multi-terminal capacitor structure. The substrate includes a wiring structure. The first semiconductor die and the second semiconductor die are disposed over the substrate. The multi-terminal capacitor structure is embedded in the substrate. The multi-terminal capacitor structure includes a first positive terminal and a first ground terminal which are electrically coupled to the first semiconductor die through the wiring structure. The multi-terminal capacitor structure also includes a second positive terminal and a second ground terminal which are electrically coupled to the second semiconductor die through the wiring structure.Type: ApplicationFiled: November 29, 2021Publication date: July 7, 2022Inventors: Chang Liang, Jinghao Chen, Zhigang Duan, Kuei-Ti Chan
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Publication number: 20210384291Abstract: A semiconductor package includes a first die comprising an upper surface and a lower surface opposite to the upper surface. The first die includes a plurality of through-silicon vias (TSVs) penetrating through the first die. A second die is stacked on the upper surface of the first die. An interposer layer is disposed on the lower surface of the first die. An inductor is disposed in the interposer layer. The inductor comprises terminals directly coupled to the TSVs.Type: ApplicationFiled: May 12, 2021Publication date: December 9, 2021Inventors: Zheng Zeng, Ching-Chung Ko, Kuei-Ti Chan
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Patent number: 9947624Abstract: The invention provides a semiconductor package assembly with a TSV interconnect. The semiconductor package assembly includes a first semiconductor package mounted on a base, having: a semiconductor die, a semiconductor substrate, and a first array of TSV interconnects and a second array of TSV interconnects formed through the semiconductor substrate, wherein the first array and second array of TSV interconnects are separated by an interval region. The assembly further includes a second semiconductor die mounted on the first semiconductor package, having a ground pad thereon. One of the TSV interconnects of the first semiconductor package has a first terminal coupled to the ground pad of the second semiconductor die and a second terminal coupled to an interconnection structure disposed on a front side of the semiconductor substrate.Type: GrantFiled: December 29, 2016Date of Patent: April 17, 2018Assignee: MediaTek Inc.Inventors: Ming-Tzong Yang, Cheng-Chou Hung, Wei-Che Huang, Yu-Hua Huang, Tzu-Hung Lin, Kuei-Ti Chan, Ruey-Beei Wu, Kai-Bin Wu
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Publication number: 20170110406Abstract: The invention provides a semiconductor package assembly with a TSV interconnect. The semiconductor package assembly includes a first semiconductor package mounted on a base, having: a semiconductor die, a semiconductor substrate, and a first array of TSV interconnects and a second array of TSV interconnects formed through the semiconductor substrate, wherein the first array and second array of TSV interconnects are separated by an interval region. The assembly further includes a second semiconductor die mounted on the first semiconductor package, having a ground pad thereon. One of the TSV interconnects of the first semiconductor package has a first terminal coupled to the ground pad of the second semiconductor die and a second terminal coupled to an interconnection structure disposed on a front side of the semiconductor substrate.Type: ApplicationFiled: December 29, 2016Publication date: April 20, 2017Inventors: Ming-Tzong YANG, Cheng-Chou HUNG, Wei-Che HUANG, Yu-Hua HUANG, Tzu-Hung LIN, Kuei-Ti CHAN, Ruey-Beei WU, Kai-Bin WU
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Patent number: 9570399Abstract: The invention provides a semiconductor package assembly with a TSV interconnect. The semiconductor package assembly includes a first semiconductor die mounted on a base. The first semiconductor die includes a semiconductor substrate. A first array of TSV interconnects and a second array of TSV interconnects are formed through the semiconductor substrate, wherein the first array and second array of TSV interconnects are separated by an interval region. A first ground TSV interconnect is disposed within the interval region. A second semiconductor die is mounted on the first semiconductor die, having a ground pad thereon. The first ground TSV interconnect of the first semiconductor die has a first terminal coupled to the ground pad of the second semiconductor die and a second terminal coupled to an interconnection structure disposed on a front side of the semiconductor substrate.Type: GrantFiled: December 9, 2015Date of Patent: February 14, 2017Assignee: MediaTek Inc.Inventors: Ming-Tzong Yang, Cheng-Chou Hung, Wei-Che Huang, Yu-Hua Huang, Tzu-Hung Lin, Kuei-Ti Chan, Ruey-Beei Wu, Kai-Bin Wu
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Patent number: 9548271Abstract: A semiconductor package includes a substrate, a first passivation layer disposed on the substrate, and an under bump metallurgy layer disposed on the first passivation layer. An additional under bump metallurgy layer is disposed on the first passivation layer, isolated from the under bump metallurgy layer; and a conductive pillar disposed on the additional under bump metallurgy layer.Type: GrantFiled: November 4, 2015Date of Patent: January 17, 2017Assignee: MEDIATEK INC.Inventors: Kuei-Ti Chan, Tzu-Hung Lin, Ching-Liou Huang
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Publication number: 20160181201Abstract: The invention provides a semiconductor package assembly with a TSV interconnect. The semiconductor package assembly includes a first semiconductor die mounted on a base. The first semiconductor die includes a semiconductor substrate. A first array of TSV interconnects and a second array of TSV interconnects are formed through the semiconductor substrate, wherein the first array and second array of TSV interconnects are separated by an interval region. A first ground TSV interconnect is disposed within the interval region. A second semiconductor die is mounted on the first semiconductor die, having a ground pad thereon. The first ground TSV interconnect of the first semiconductor die has a first terminal coupled to the ground pad of the second semiconductor die and a second terminal coupled to an interconnection structure disposed on a front side of the semiconductor substrate.Type: ApplicationFiled: December 9, 2015Publication date: June 23, 2016Inventors: Ming-Tzong YANG, Cheng-Chou HUNG, Wei-Che HUANG, Yu-Hua HUANG, Tzu-Hung LIN, Kuei-Ti CHAN, Ruey-Beei WU, Kai-Bin WU
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Publication number: 20160056105Abstract: A semiconductor package includes a substrate, a first passivation layer disposed on the substrate, and an under bump metallurgy layer disposed on the first passivation layer. An additional under bump metallurgy layer is disposed on the first passivation layer, isolated from the under bump metallurgy layer; and a conductive pillar disposed on the additional under bump metallurgy layer.Type: ApplicationFiled: November 4, 2015Publication date: February 25, 2016Inventors: Kuei-Ti CHAN, Tzu-Hung LIN, Ching-Liou HUANG
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Patent number: 9209148Abstract: A semiconductor package includes a substrate, a first passivation layer disposed on the substrate, and an under bump metallurgy layer disposed on the first passivation layer. A passive device is disposed on the under bump metallurgy layer, and an additional under bump metallurgy layer is disposed on the first passivation layer, isolated from the under bump metallurgy layer. A conductive pillar is disposed on the additional under bump metallurgy layer, wherein the conductive pillar and the passive device are at the same level.Type: GrantFiled: March 20, 2015Date of Patent: December 8, 2015Assignee: MEDIATEK INC.Inventors: Kuei-Ti Chan, Tzu-Hung Lin, Ching-Liou Huang
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Publication number: 20150194403Abstract: A semiconductor package includes a substrate, a first passivation layer disposed on the substrate, and an under bump metallurgy layer disposed on the first passivation layer. A passive device is disposed on the under bump metallurgy layer, and an additional under bump metallurgy layer is disposed on the first passivation layer, isolated from the under bump metallurgy layer. A conductive pillar is disposed on the additional under bump metallurgy layer, wherein the conductive pillar and the passive device are at the same level.Type: ApplicationFiled: March 20, 2015Publication date: July 9, 2015Inventors: Kuei-Ti CHAN, Tzu-Hung LIN, Ching-Liou HUANG
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Patent number: 8987897Abstract: The invention provides a semiconductor package. The semiconductor package includes a substrate. A first passivation layer is disposed on the substrate. An under bump metallurgy layer is disposed on the first passivation layer. A passive device is disposed on the under bump metallurgy layer.Type: GrantFiled: May 17, 2011Date of Patent: March 24, 2015Assignee: Mediatek Inc.Inventors: Kuei-Ti Chan, Tzu-Hung Lin, Ching-Liou Huang
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Patent number: 8860544Abstract: An integrated inductor includes a winding consisting of an aluminum layer atop a passivation layer, wherein the aluminum layer does not extend into the passivation layer and has a thickness that is not less than about 2.0 micrometers. The passivation layer has a thickness not less than about 0.8 micrometers. By eliminating copper from the integrated inductor and increasing the thickness of the passivation layer, the distance between the bottom surface of the inductor structure and the main surface of the semiconductor substrate is increased, thus the parasitic substrate coupling may be reduced and the Q-factor may be improved. Besides, the increased thickness of the aluminum layer may help improve the Q-factor as well.Type: GrantFiled: June 29, 2009Date of Patent: October 14, 2014Assignee: Mediatek Inc.Inventors: Ching-Chung Ko, Tung-Hsing Lee, Kuei-Ti Chan, Tao Cheng, Ming-Tzong Yang
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Publication number: 20130002375Abstract: A transmission line structure is disclosed. The structure includes at least one signal transmission line and a pair of ground transmission lines embedded in a first level of a dielectric layer on a substrate, wherein the pair of ground transmission lines are on both sides of the signal transmission line. A first ground layer is embedded in a second level lower than the first level of the dielectric layer and a second ground layer is embedded in a third level higher than the first level of the dielectric layer. First and second pairs of via connectors are embedded in the dielectric layer, wherein the first pair of via connectors electrically connects the pair of ground transmission lines to the first ground layer and the second pair of via connectors electrically connects the pair of ground transmission lines to the second ground layer.Type: ApplicationFiled: July 1, 2011Publication date: January 3, 2013Applicant: MEDIATEK INC.Inventors: Ming-Tzong Yang, Tung-Hsing Lee, Kuei-Ti Chan
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Publication number: 20120126368Abstract: The invention provides a semiconductor package. The semiconductor package includes a substrate. A first passivation layer is disposed on the substrate. An under bump metallurgy layer is disposed on the first passivation layer.Type: ApplicationFiled: May 17, 2011Publication date: May 24, 2012Applicant: MEDIATEK INC.Inventors: Kuei-Ti Chan, Tzu-Hung Lin, Ching-Liou Huang
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Publication number: 20110133308Abstract: A semiconductor device includes a substrate; an inductor wiring pattern overlying the substrate, wherein the inductor wiring pattern is formed in an inductor-forming region; a plurality of shielding patterns between the inductor wiring pattern and the substrate within the inductor-forming region; and at least one first oxide define (OD) pattern disposed in the substrate or between the inductor wiring pattern and the substrate.Type: ApplicationFiled: February 16, 2011Publication date: June 9, 2011Inventors: Kuei-Ti Chan, Tung-Hsing Lee, Augusto Marques, Wen-Chang Lee
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Publication number: 20100295150Abstract: A semiconductor device includes a substrate, an inductor wiring pattern on the substrate, and at least one oxide define (OD) dummy feature disposed in the substrate under the inductor wiring pattern.Type: ApplicationFiled: February 11, 2010Publication date: November 25, 2010Inventors: Kuei-Ti Chan, Tung-Hsing Lee
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Publication number: 20090261937Abstract: An integrated inductor includes a winding consisting of an aluminum layer atop a passivation layer, wherein the aluminum layer does not extend into the passivation layer and has a thickness that is not less than about 2.0 micrometers. The passivation layer has a thickness not less than about 0.8 micrometers. By eliminating copper from the integrated inductor and increasing the thickness of the passivation layer, the distance between the bottom surface of the inductor structure and the main surface of the semiconductor substrate is increased, thus the parasitic substrate coupling may be reduced and the Q-factor may be improved. Besides, the increased thickness of the aluminum layer may help improve the Q-factor as well.Type: ApplicationFiled: June 29, 2009Publication date: October 22, 2009Inventors: Ching-Chung Ko, Tung-Hsing Lee, Kuei-Ti Chan, Tao Cheng, Ming-Tzong Yang