Patents by Inventor Kuei-Wu Chu
Kuei-Wu Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150235978Abstract: Electroless nickel bumps of die pads and a method thereof are disclosed. A protection layer is formed on the top surface and a surrounding sidewall of each electroless nickel bump in turn or at the same time by two separated processes or the same process. The two separated processes are selected from the group consisting of immersion gold and immersion silver. Thereby hardness of the top surface of the electroless nickel bump is improved and reduced. Moreover, easy oxidation of the surrounding sidewall of the electroless nickel bump and short circuit of the bump caused by electron migration can both be avoided.Type: ApplicationFiled: July 5, 2012Publication date: August 20, 2015Inventors: Ta-Lun Sung, Kuei-Wu Chu, Tung-Sheng Lai
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Patent number: 8424357Abstract: A die includes upper contacts, lower contacts and conductive elements. The upper contacts are formed on an upper face of the die. The upper contacts include a non-connected upper contact and connected upper contacts. The lower contacts are formed on a lower face of the die. The lower contacts include a non-connected lower contact and connected lower contacts. Each of the conductive elements connects a related one of the connected upper contacts to a related one of the connected lower contacts.Type: GrantFiled: June 8, 2010Date of Patent: April 23, 2013Assignee: Aflash Technology Co., Ltd.Inventors: Leo Lu, Kuei-Wu Chu, Jimmy Liang
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Patent number: 8299629Abstract: A wafer-bump structure includes a wafer-state semiconductor die, a pre-treatment layer, a first ENIG laminate and at least one pillar bump. The wafer-state semiconductor die includes at least one die pad embedded therein and a passivation layer formed on the wafer-state semiconductor die and the die pad. The passivation layer includes an aperture for allowing access to a portion of the die pad. The pre-treatment layer is formed on the un-covered portion of the die pad. The first ENIG laminate is formed on the pre-treatment layer and an annular portion of the passivation layer around the pre-treatment layer. The pillar bump includes a conductive metal layer and a second ENIG laminate. The conductive metal layer is formed on the first ENIG laminate and another annular portion of the passivation layer around the first ENIG laminate. The second ENIG laminate is formed on the conductive metal layer and another annular portion of the passivation layer around the conductive metal layer.Type: GrantFiled: April 11, 2011Date of Patent: October 30, 2012Assignee: Aflash Technology Co., Ltd.Inventors: Kuei-Wu Chu, Tse Ming Chu
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Publication number: 20120181065Abstract: A multi-layered circuit board device includes an isolative layer and a wiring layer sequentially provided on a circuit board in a PCB, ceramic, LTCC or aluminum nitride build-up process. Thus, the thickness of the multi-layered circuit board device is small and the density of the multi-layered the circuit board device is high. Furthermore, the structure of the multi-layered circuit board device is simple and the cost of the multi-layered circuit board device is low. The layers are connected to one another in the PCB, ceramic, LTCC or aluminum nitride build-up process without having to use additional alignment target points.Type: ApplicationFiled: June 15, 2011Publication date: July 19, 2012Applicant: MAO BANG ELECTRONIC CO., LTD.Inventor: Kuei-Wu Chu
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Patent number: 8184464Abstract: A flash memory includes a controller unit and dies. The dies are connected to a controller unit. Each of the dies includes an upper face and a lower face. Each of the dies includes at least one power supply pad, at least one grounding pad, at least one input/output pad, selection pads and standby/busy pads on each of the upper and lower faces. The power supply pad is connected to the controller unit. The grounding pad is connected to the power supply pad in parallel. The input/output pad is connected to the grounding pad in parallel. The selection pads are connected to the controller unit and connected to one another with a wire that can be cut if so desired. The standby/busy pads are connected to the controller unit and connected to one another with a wire that can be cut if so desired.Type: GrantFiled: May 14, 2010Date of Patent: May 22, 2012Assignee: Aflash Technology, Co., Ltd.Inventors: Kuei-Wu Chu, Jimmy Liang, Leo Lu
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Publication number: 20120074558Abstract: A package of a circuit board and a die are packed through surface mount technology (SMT). The shortest circuit is formed with at a low cost. Thus, the package can work in high speed and high frequency applications.Type: ApplicationFiled: March 7, 2011Publication date: March 29, 2012Applicant: MAO BANG ELECTRONIC CO., LTD.Inventors: Hsuan Yu LU, Tse Ming CHU, Kuei-Wu CHU
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Publication number: 20110260300Abstract: A wafer-bump structure includes a wafer-state semiconductor die, a pre-treatment layer, a first ENIG laminate and at least one pillar bump. The wafer-state semiconductor die includes at least one die pad embedded therein and a passivation layer formed on the wafer-state semiconductor die and the die pad. The passivation layer includes an aperture for allowing access to a portion of the die pad. The pre-treatment layer is formed on the un-covered portion of the die pad. The first ENIG laminate is formed on the pre-treatment layer and an annular portion of the passivation layer around the pre-treatment layer. The pillar bump includes a conductive metal layer and a second ENIG laminate. The conductive metal layer is formed on the first ENIG laminate and another annular portion of the passivation layer around the first ENIG laminate. The second ENIG laminate is formed on the conductive metal layer and another annular portion of the passivation layer around the conductive metal layer.Type: ApplicationFiled: April 11, 2011Publication date: October 27, 2011Applicant: MAO BANG ELECTRONIC CO., LTD.Inventors: Kuei-Wu Chu, Tse Ming Chu
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Publication number: 20110108983Abstract: An integrated circuit includes a die including contacts formed thereon. A first dielectric layer is formed on the die. The first dielectric layer includes apertures defined therein corresponding to the contacts. A second dielectric layer is formed on the second dielectric layer. The second dielectric layer includes apertures defined therein corresponding to the apertures of the first dielectric layer. Redistribution layers are located in the apertures of the first and second dielectric layers and connected to the contacts. A passivation layer is located on the second dielectric layer and the redistribution layers. The passivation layer includes apertures corresponding to the redistribution layers. A solder ball is located in each of the apertures of the passivation layer and connected to a related one of the redistribution layers.Type: ApplicationFiled: July 8, 2010Publication date: May 12, 2011Applicant: MAO BANG ELECTRONIC CO., LTD.Inventors: Leo Lu, Kuei-Wu Chu, Jimmy Liang
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Publication number: 20110062586Abstract: A chip includes a device, a passivation layer, two dielectric layers, at least one upper redistribution layer, at least one lower redistribution layer, at least one tunnel, at least one conductor, a redistribution passivation layer and at least one solder ball. The device includes at least one pad. The tunnel is defined in the upper redistribution layer, the first dielectric layer, the passivation layer, the pad, the device, the chip, the second dielectric layer and the lower redistribution layer. The conductor is located in the tunnel and connected to the upper and lower redistribution layers. The redistribution passivation layer is located on the second dielectric layer, the lower redistribution layer and the conductor. The solder ball is located on a portion of the lower redistribution layer through an aperture defined in the redistribution passivation layer. The chip can be connected to a printed circuit board by the solder ball.Type: ApplicationFiled: June 13, 2010Publication date: March 17, 2011Applicant: MAO BANG ELECTRONIC CO., LTD.Inventors: Leo Lu, Kuei-Wu Chu, Jimmy Liang
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Publication number: 20110062590Abstract: A chip stacking device uses nano particle silver paste for re-distribution interconnection to form a structure having low resistance through trench filling or printing. Thus, due to its low resistance, it can effectively reduce the electrical instability due to voltage drop after current flows. Furthermore, power consumption is reduced too, with energy saved. With its stable electrical signal, its utilization scope can be further expanded to high frequency product.Type: ApplicationFiled: July 8, 2010Publication date: March 17, 2011Applicant: MAO BANG ELECTRONIC CO., LTD.Inventors: Leo Lu, Kuei-Wu Chu, Jimmy Liang
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Publication number: 20110023574Abstract: A die includes upper contacts, lower contacts and conductive elements. The upper contacts are formed on an upper face of the die. The upper contacts include a non-connected upper contact and connected upper contacts. The lower contacts are formed on a lower face of the die. The lower contacts include a non-connected lower contact and connected lower contacts. Each of the conductive elements connects a related one of the connected upper contacts to a related one of the connected lower contacts.Type: ApplicationFiled: June 8, 2010Publication date: February 3, 2011Applicant: MAO BANG ELECTRONIC CO., LTD.Inventors: Leo Lu, Kuei-Wu Chu, Jimmy Liang
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Publication number: 20110019457Abstract: A flash memory includes a controller unit and dies. The dies are connected to a controller unit. Each of the dies includes an upper face and a lower face. Each of the dies includes at least one power supply pad, at least one grounding pad, at least one input/output pad, selection pads and standby/busy pads on each of the upper and lower faces. The power supply pad is connected to the controller unit. The grounding pad is connected to the power supply pad in parallel. The input/output pad is connected to the grounding pad in parallel. The selection pads are connected to the controller unit and connected to one another with a wire that can be cut if so desired. The standby/busy pads are connected to the controller unit and connected to one another with a wire that can be cut if so desired.Type: ApplicationFiled: May 14, 2010Publication date: January 27, 2011Applicant: MAO BANG ELECTRONIC CO., LTD.Inventors: Kuei-Wu Chu, Jimmy Liang, Leo Lu