Abstract: A method of fabricating ROM products through the use of embedded flash/EEPROM prototypes is disclosed. This is accomplished by first forming a Flash/EEPROM prototype, performing programming simulations on the prototype, developing a ROM code and mask, and then forming a ROM product in the same manufacturing line by skipping certain Flash/EEPROM steps and then implanting the ROM code into the final ROM product. The method improves turn-around-time in the manufacturing line, and reduces cost to the customer. A method of doing business is also disclosed directed to providing ROM products to a customer without much redesign time and effort on the part of the customer.

Abstract: A method to form shallow trench isolations with reduced substrate defects by using a nitrogen anneal is achieved. A silicon substrate is provided. The silicon substrate is etched where not protected by a photoresist mask to form shallow trenches where shallow trench isolations are planned. A liner oxide layer is grown on the interior surfaces of the shallow trenches. The silicon substrate and the liner oxide layer are annealed to reduce or eliminate defects, dislocations, interface traps, and stress in the silicon substrate. An isolation oxide layer is deposited overlying the liner oxide layer and completely filling the shallow trenches. The isolation oxide layer is etched down to the top surface of the silicon substrate and thereby forms the shallow trench isolations. The integrated circuit device is completed.

Abstract: A method for filling a trench within a substrate. First a substrate is provided having a trench formed therein. The trench has a bottom surface and opposing side walls. An undoped silicon glass liner is then thermally grown to coat the bottom surface and side walls of the trench. An undoped silicon oxide layer is then deposited over the undoped silicon glass liner. A boron doped silicon oxide layer is then deposited over the undoped silicon oxide layer, filling the trench. The boron doped silicon oxide layer is then heated to reflow the boron doped silicon oxide to fill any void initially formed within the boron doped silicon oxide layer within the trench, thereby eliminating any void so formed.

Abstract: Current aqueous methods for removal of polymeric materials from the sidewalls of trenches etched into silicon wafers by reactive-ion-etching are inadequate for treating deep trenches having high aspect ratios. Spin-dry operations performed after the aqueous etching are incapable of completely removing rinse water and ionic species from these deep trenches, thereby leaving pockets of liquid. Subsequent evaporation of these pockets results in the concentration and eventual precipitation of residual ionic species creating watermarks. A two stage cleaning method is described in which the first stage dissolves the sidewall polymer and the second stage draws ionic species strongly chemisorbed onto the silicon surfaces into solution. A key feature of the method is that the wafer surface is not permitted to dry until after the final rinse.

Abstract: A method for forming an improved trench isolation having a conformal liner oxide and rounded top and bottom corners in the trench was achieved. The conformal liner oxide improves the CVD gap-filling capabilities for these deep submicron wide trenches, and the rounded corners improve the electrical characteristics of the devices in the adjacent device areas. After etching trenches with vertical sidewalls in the silicon substrate, a two-step oxidation process is used to form the conformal liner oxide. A first oxidation step using a low-oxygen flow rate and a low temperature (about 850 to 920.degree. C.) is used to achieve rounded bottom corners. A second oxidation step at a low-oxygen flow rate and a higher temperature (about 1000 to 1150.degree. C.) is used to achieve rounded top corners. The two-step process also results in a more conformal liner oxide.

Abstract: This invention relates to the characterization of integrated circuit devices and more particularly to an improved method for monitoring for unacceptable kink behavior, in the threshold voltage characteristics of FET devices, that can be caused by a tendency for reduced gate oxide thickness and reduced substrate doping concentration, along the length of channel regions bounded by STI. This is achieved by comparing a pair of drain current versus gate voltage characteristics, as a function of two values of substrate voltage. Relative voltage shifts between the two curves are compared at a value of drain current that is well below the kink and at a value of drain current that is well above the kink. The quantitative degree of kink behavior is determined by how much greater the voltage shift, corresponding to the value of drain current well above the kink, exceeds the voltage shift, corresponding to the value of drain current well below the kink.

Abstract: A new method for planarization of shallow trench isolation is disclosed by using a polysilicon layer to prevent trench formed in a silicon nitride layer. The formation of the shallow trench isolation described herein includes a pad layer and a silicon nitride layer formed on a semiconductor wafer. A polysilicon layer is subsequently formed on the silicon nitride layer. A shallow trench is then created by photolithography and dry etching processes. The photoresist is subsequently removed in which an oxide layer is form in the shallow trench and on polysilicon layer for the purpose of isolation. A selective etching is used to etch the oxide layer. A CMP is performed to produce a planarized surface on a silicon wafer.

Abstract: A new method for planarizing a shallow trench isolation is disclosed by using a polysilicon layer or bottom anti-reflective coating (BARC) to form a reverse tone with a taper profile. The formation of the shallow trench isolation described includes a pad layer, and a silicon nitride layer formed-on a semiconductor wafer. Trenches are created by photolithography and dry etching processes. An oxide layer is formed in the trenches for the purpose of isolation. A polysilicon layer or bottom anti-reflective coating is subsequently formed on the oxide layer. A plurality of openings are generated in the polysilicon or the BARC layer. An etching is used to etch the oxide layer, thereby forming a reverse tone having a taper profile. A Chemical Mechanical Polishing is performed to planarize the surface of a semiconductor wafer.

Abstract: A new method of metallization without unwanted precipitates using a tungsten plug is achieved. Semiconductor device structures are formed in and on a semiconductor substrate. A contact hole is opened through an insulating layer to the semiconductor substrate. A glue layer is deposited conformally over the surface of the insulating layer and within the contact opening. A layer of tungsten is blanket deposited over the glue layer. The tungsten layer is etched back leaving the tungsten only within the contact opening to form a tungsten plug. The etching back leaves impurities on the surface of the glue layer. Those impurities will react with water or air to form precipitates. The precipitates are removed using a wet chemical etch. The substrate is post treated with argon ion sputtering to prevent future formation of precipitates.