Patents by Inventor Kuei-Yuam Hsu

Kuei-Yuam Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method to prevent passivation layer peeling in a solder bump formation process
    Patent number: 6951803
    Abstract: A method for reducing peeling of a cross-linked polymer passivation layer in a solder bump formation process including providing a multi-level semiconductor device formed on a semiconductor process wafer having an uppermost surface comprising a metal bonding pad in electrical communication with underlying device levels; forming a layer of resinous pre-cursor polymeric material over the process surface said resinous polymeric material having a glass transition temperature (Tg) upon curing; subjecting the semiconductor process wafer to a pre-curing thermal treatment temperature below Tg for a period of time; and, subjecting the semiconductor process wafer to at least one subsequent thermal treatment temperature above Tg for a period of time to form an uppermost passivation layer.
    Type: Grant
    Filed: February 26, 2004
    Date of Patent: October 4, 2005
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kai Tzeng, Cheng-Ming Wu, Chu-Wei Hu, Jung-Lieh Hsu, Kuei-Yuam Hsu
  • METHOD TO PREVENT PASSIVATION LAYER PEELING IN A SOLDER BUMP FORMATION PROCESS
    Publication number: 20050191836
    Abstract: A method for reducing peeling of a cross-linked polymer passivation layer in a solder bump formation process including providing a multi-level semiconductor device formed on a semiconductor process wafer having an uppermost surface comprising a metal bonding pad in electrical communication with underlying device levels; forming a layer of resinous pre-cursor polymeric material over the process surface said resinous polymeric material having a glass transition temperature (Tg) upon curing; subjecting the semiconductor process wafer to a pre-curing thermal treatment temperature below Tg for a period of time; and, subjecting the semiconductor process wafer to at least one subsequent thermal treatment temperature above Tg for a period of time to form an uppermost passivation layer.
    Type: Application
    Filed: February 26, 2004
    Publication date: September 1, 2005
    Inventors: Kai Tzeng, Cheng-Ming Wu, Chu-Wei Hu, Jung-Lieh Hsu, Kuei-Yuam Hsu