Abstract: A card reader with power-saving function is used for being inserted with a memory card so that a computer can access the memory card through the card reader. When the memory card is inserted in the card reader, the card reader is enabled to operate. On the other hand, when the memory card is not inserted in the card reader, the card reader enters to a power-down mode for saving power.

Abstract: A card reader with power-saving function is used for being inserted with a memory card so that a computer can access the memory card through the card reader. When the memory card is inserted in the card reader, the card reader is enabled to operate. On the other hand, when the memory card is not inserted in the card reader, the card reader enters to a power-down mode for saving power.

Abstract: A method for dynamically managing a removable device includes the following steps: generating a device insertion interrupt to indicate that the removable device has been coupled to a connection interface when detecting an insert event corresponding to the removable device; clearing the device insertion interrupt before a processing mechanism corresponding to the connection interface handles the device insertion interrupt; and identifying a specification of the removable device to dynamically manage the removable device according to the specification; wherein when the specification corresponds to a first specification, a first management scheme is activated to manage the removable device, when the specification corresponds to a second specification, a second management scheme is activated to manage the removable device, and the first specification is different from the second specification.

Abstract: Disclosed is an adjusting circuit for determining a target delay clock signal of a delay circuit having a plurality of delay units. The delay circuit generates a plurality of delay clock signals, and the adjusting circuit includes: a difference signal generating circuit, for generating a plurality of difference signals according to a reference clock signal and the delay clock signals; a delay processing circuit, coupled to the difference signal generating circuit, for determining the target delay clock signal by computing a corresponding number of delay units for a specific phase of the reference clock signal according to the difference signals; wherein the target delay clock signal is one of the delay clock signals.

Abstract: The invention discloses an arbiter for arbitrating the mastership of a bus. The bus is coupled to a plurality of masters. The arbiter includes a request detection unit, a latency count unit, a grant generation unit, and an arbitration control unit. The request detection unit is used for detecting a plurality of request signals corresponding to the masters. According to a latency cycle of each request signal, the latency count unit counts the decayed latency of each request signal and further compares the decayed latency of each request signal, so as to determine the level of priority given to a designated master. Accordingly, the arbitration control unit is configured to control the grant generation unit to selectively generate a grant signal, such that the designated master with a higher level of priority will obtain the mastership of the bus based on the grant signal.

Abstract: Disclosed is an adjusting circuit for determining a target delay clock signal of a delay circuit having a plurality of delay units. The delay circuit generates a plurality of delay clock signals, and the adjusting circuit includes: a difference signal generating circuit, for generating a plurality of difference signals according to a reference clock signal and the delay clock signals; a delay processing circuit, coupled to the difference signal generating circuit, for determining the target delay clock signal by computing a corresponding number of delay units for a specific phase of the reference clock signal according to the difference signals; wherein the target delay clock signal is one of the delay clock signals.