Abstract: Provided is a semiconductor memory device including a plurality of memory banks. Each of the memory banks includes a first memory cell, a second memory cell, a select circuit, and a decoding circuit. The select circuit is respectively coupled to the first and second memory cells through first and second bit lines, and selects the memory cell to be operated according to a first switch signal and a second switch signal. The decoding circuit generates the first switch signal and the second switch signal according to a memory-bank select signal, a first local column select signal, and a second local column select signal.

Abstract: A memory apparatus and an initialization method thereof are provided. The initialization method includes the following steps. A power-up operation is performed on the memory apparatus to provide an internal voltage to a memory array. After the internal voltage is stabilize, a refresh operation is performed on all storage cells.

Abstract: A memory apparatus and an initialization method thereof are provided. The initialization method includes the following steps. A power-up operation is performed on the memory apparatus to provide an internal voltage to a memory array. After the internal voltage is stabilize, a refresh operation is performed on all storage cells.

Abstract: A memory storage device and a memory testing method for testing a memory array of the memory storage device are provided. The memory testing method includes the following steps: writing first data into a plurality of first segments of the memory array, and writing second data to a second segment of the memory array; obtaining third data by reading the plurality of first segments, and obtaining fourth data by reading the second segment; converting the fourth data to fifth data, wherein the fifth data is the same as check data obtained by encoding the first data by using an encoding circuit corresponding to a decoding circuit of the memory storage device.

Abstract: An internal voltage generating apparatus is provided. A regulating unit detects whether an internal voltage is lower than a threshold voltage, and outputs a compensation current provided by a first power pad to a second power line connected with a second power pad when the internal voltage is lower than the threshold voltage, so as to regulate the internal voltage provided by the internal voltage generating apparatus.

Abstract: Semiconductor memories are provided. The Semiconductor memory includes a plurality of sense amplifiers, plurality sets of master data line segments and a plurality of memory segments. The plurality sets of master data line segments are arranged in a column direction. Each memory segment includes a plurality of memory cells, and is coupled to a set of corresponding master data line segments via a corresponding sense amplifier. Adjacent sets of corresponding master data line segments are coupled together. When accessing memory data, the memory data are transferred by the adjacent sets of corresponding master data line segments which are coupled together.

Abstract: An internal voltage generating apparatus is provided. A regulating unit detects whether an internal voltage is lower than a threshold voltage, and outputs a compensation current provided by a first power pad to a second power line connected with a second power pad when the internal voltage is lower than the threshold voltage, so as to regulate the internal voltage provided by the internal voltage generating apparatus.

Abstract: Semiconductor memories are provided. The Semiconductor memory includes a plurality of sense amplifiers, plurality sets of master data line segments and a plurality of memory segments. The plurality sets of master data line segments are arranged in a column direction. Each memory segment includes a plurality of memory cells, and is coupled to a set of corresponding master data line segments via a corresponding sense amplifier. Adjacent sets of corresponding master data line segments are coupled together. When accessing memory data, the memory data are transferred by the adjacent sets of corresponding master data line segments which are coupled together.

Abstract: A dynamic random access memory (DRAM) unit and a data refreshing method thereof are provided. The DRAM unit includes a memory array, a refresh address module, and a refresh control module. The memory array includes multiple memory cells. The refresh address module produces a refresh word line address cyclically during a refresh mode. The refresh control module coupled to the memory array and the refresh address module obtains a start word line address and a stop word line address corresponding to the start word line address to form a memory word line address interval. Then, the refresh control module determines that the refresh word line address is within the memory word line address interval to execute a data charging operation to the memory cells corresponding to the refresh word line address, or stop the data charging operation otherwise, so as to reduce power consumption during the refresh mode.

Abstract: A dynamic random access memory (DRAM) unit and a data refreshing method thereof are provided. The DRAM unit includes a memory array, a refresh address module, and a refresh control module. The memory array includes multiple memory cells. The refresh address module produces a refresh word line address cyclically during a refresh mode. The refresh control module coupled to the memory array and the refresh address module obtains a start word line address and a stop word line address corresponding to the start word line address to form a memory word line address interval. Then, the refresh control module determines that the refresh word line address is within the memory word line address interval to execute a data charging operation to the memory cells corresponding to the refresh word line address, or stop the data charging operation otherwise, so as to reduce power consumption during the refresh mode.

Abstract: A circuit for generating a current that comprises a first current generator providing a constant current in response to a constant voltage, a voltage generator providing a temperature dependent voltage, and a second current generator coupled to the voltage generator providing a variable current in response to the temperature dependent voltage.