Abstract: A dynamic secret key security system for test circuit and a method of the same are disclosed. The security architecture includes a scan chain set, a dynamic key generator, a secret key checking logic, a fake response generator, and a controller. Scan chains of the scan chain set receive a test vector while the dynamic key generator produces different secret keys according to the test vector received. The secret key checking logic is used for comparing the test vector with the secret key so as to know whether they are the same. Thus whether the test vector being input is legal can be learned. Thereby the present dynamic secret key generation technique provides higher security level. Moreover, the secret key will not be stored in the memory in advance so that attackers cannot get the secret key through attacks on the memory.

Abstract: A test decompressor and a test method thereof for converting original input data of one single test input into test vectors for testing a circuit under test (CUT) containing scan chains are revealed. The test decompressor includes a test data spreader, a test configuration switch, and a test controller. The test data spreader converts the original input data into a plurality of test data. The test configuration switch receives the original input data and the plurality of test data and transfers these data to scan chains of the CUT. The test controller receives the original input data and outputs a select signal to the test configuration switch for switching current test configuration to another test configuration. The scan chains in the CUT are divided into several scan groups and the scan chains in each scan group share the same test data. Thus the test data volume can be significantly reduced.

Abstract: An integrated circuit (IC) automatic test system and an IC automatic test method storing test data in scan chains are revealed. The automatic test system includes at least one scan chain, a test controller and a test decompressor connected. Each scan chain consists of a storage portion with a plurality of scan units and a scan input corrector. The storage portion is for storing test data and the scan input corrector is used to adjust test patterns to be shifted into the scan chains. The test controller is for control of test flow while the test decompressor reconstructs and decompresses the test data stored in the storage portions of the scan chains to generate test patterns for the circuit under test. Thereby the IC electrical test is performed automatically and the test cost and the test cost is reduced.

Abstract: A test decompressor and a test method thereof for converting original input data of one single test input into test vectors for testing a circuit under test (CUT) containing scan chains are revealed. The test decompressor includes a test data spreader, a test configuration switch, and a test controller. The test data spreader converts the original input data into a plurality of test data. The test configuration switch receives the original input data and the plurality of test data and transfers these data to scan chains of the CUT. The test controller receives the original input data and outputs a select signal to the test configuration switch for switching current test configuration to another test configuration. The scan chains in the CUT are divided into several scan groups and the scan chains in each scan group share the same test data. Thus the test data volume can be significantly reduced.

Abstract: An integrated circuit (IC) automatic test system and an IC automatic test method storing test data in scan chains are revealed. The automatic test system includes at least one scan chain, a test controller and a test decompressor connected. Each scan chain consists of a storage portion with a plurality of scan units and a scan input corrector. The storage portion is for storing test data and the scan input corrector is used to adjust test patterns to be shifted into the scan chains. The test controller is for control of test flow while the test decompressor reconstructs and decompresses the test data stored in the storage portions of the scan chains to generate test patterns for the circuit under test. Thereby the IC electrical test is performed automatically and the test cost and the test cost is reduced.

Abstract: A system and a method for temperature sensing of three-dimensional integrated circuits are revealed. The three-dimensional integrated circuit is formed by stacking of a plurality of chip layers that execute specific functions. The chip layer includes a master layer and at least one slave layer. The master layer is disposed with a master temperature sensor while a first thermal conductive part is arranged at the slave layer where heat is detected. The first thermal conductive part and the master temperature sensor are connected by a thermal conductive structure. Thereby temperature of various points at different chip layers is conducted to the same chip layer by Through Silicon Vias to be measured and calibrated. The design complexity and the implementation cost of the temperature sensing system are significantly reduced.

Abstract: A method for diagnosing a defect is provided. A first candidate pair comprises a first defect candidate and a second defect candidate. A first pattern is generated to distinguish one or more faults of the first defect candidate from one or more faults of the second defect candidate. The first defect candidate is removed responsive to determining that the first pattern does not detect the first defect candidate and determining that an automatic test equipment (ATE) failure log associates the first pattern with failure. Removing the first candidate pair, as well as additional candidate pairs when possible, promotes diagnosis efficiency by reducing a number of computations required.

Abstract: A multi-point temperature sensing method for integrated circuit chips and a system of the same are revealed. The system includes at least one slave temperature sensor embedded at preset positions for measuring temperature of a block and a master temperature sensor embedded in an integrated circuit chip and electrically connected to each slave temperature sensor. Variations of the slave temperature sensor induced by variations of process, voltage and temperature are corrected by the master temperature sensor. Thus the area the temperature sensors required on the integrated circuit chip is dramatically reduced and the stability of the temperature control system is improved. The problem of conventional System-on-a-Chip that only a limited number of temperature sensors could be used due to the area they occupied can be solved.

Abstract: A method for diagnosing a defect is provided. A first candidate pair comprises a first defect candidate and a second defect candidate. A first pattern is generated to distinguish one or more faults of the first defect candidate from one or more faults of the second defect candidate. The first defect candidate is removed responsive to determining that the first pattern does not detect the first defect candidate and determining that an automatic test equipment (ATE) failure log associates the first pattern with failure. Removing the first candidate pair, as well as additional candidate pairs when possible, promotes diagnosis efficiency by reducing a number of computations required.

Abstract: A system and a method for temperature sensing of three-dimensional integrated circuits are revealed. The three-dimensional integrated circuit is formed by stacking of a plurality of chip layers that execute specific functions. The chip layer includes a master layer and at least one slave layer. The master layer is disposed with a master temperature sensor while a first thermal conductive part is arranged at the slave layer where heat is detected. The first thermal conductive part and the master temperature sensor are connected by a thermal conductive structure. Thereby temperature of various points at different chip layers is conducted to the same chip layer by Through Silicon Vias to be measured and calibrated. The design complexity and the implementation cost of the temperature sensing system are significantly reduced.

Abstract: A multi-point temperature sensing method for integrated circuit chips and a system of the same are revealed. The system includes at least one slave temperature sensor embedded at preset positions for measuring temperature of a block and a master temperature sensor embedded in an integrated circuit chip and electrically connected to each slave temperature sensor. Variations of the slave temperature sensor induced by variations of process, voltage and temperature are corrected by the master temperature sensor. Thus the area the temperature sensors required on the integrated circuit chip is dramatically reduced and the stability of the temperature control system is improved. The problem of conventional System-on-a-Chip that only a limited number of temperature sensors could be used due to the area they occupied can be solved.

Abstract: A debugging control system using inside-core events as trigger conditions and a method of the same are revealed. The method includes following steps. First set up at least one trigger condition and a search range of the clock cycle according to internal states of a core under debug. Pause clock and recover clock of each clock cycle within the search range. Retrieve data of scan chains of the core under debug by a shift buffer during the clock pausing. Next combine data of the scan chains by a trigger comparator circuit to form trigger signals and check whether the trigger signals satisfy the trigger condition. If the trigger condition is satisfied or the trigger signal is over the search range, the clock is paused continuingly and internal states of the scan chains of the core under debug are output otherwise the core under debug is recovered.

Abstract: A debugging control system using inside-core events as trigger conditions and a method of the same are revealed. The method includes following steps. First set up at least one trigger condition and a search range of the clock cycle according to internal states of a core under debug. Pause clock and recover clock of each clock cycle within the search range. Retrieve data of scan chains of the core under debug by a shift buffer during the clock pausing. Next combine data of the scan chains by a trigger comparator circuit to form trigger signals and check whether the trigger signals satisfy the trigger condition. If the trigger condition is satisfied or the trigger signal is over the search range, the clock is paused continuingly and internal states of the scan chains of the core under debug are output otherwise the core under debug is recovered.

Abstract: A multi-project system-on-chip bench by integrating multiple system-on-chip projects into a chip, which uses a system chip bench, therefore, microprocessor, bus, embedded memory, peripheral component and input/output port is used together by those system-on-chip projects and the average cost of each system-on-chip is thus reduced. Moreover, this invention proposes a design method for multi-project system-on-chip bench, it let the user can effectively manage available data and verification environment in each design process flow hierarchy and in turn an easy-to-use design process flow is thus derived.

Abstract: A multi-project system-on-chip bench by integrating multiple system-on-chip projects into a chip, which uses a system chip bench, therefore, microprocessor, bus, embedded memory, peripheral component and input/output port is used together by those system-on-chip projects and the average cost of each system-on-chip is thus reduced. Moreover, this invention proposes a design method for multi-project system-on-chip bench, it let the user can effectively manage available data and verification environment in each design process flow hierarchy and in turn an easy-to-use design process flow is thus derived.

Abstract: A test method for a plurality of circuits respectively having inputs for greatly reducing the required test time and the control circuit complexity is provided. The method includes steps of providing a set of test patterns for detecting a characteristic of the circuits, providing a common data line, and electrically connecting the circuit inputs to the common data line so that the test pattern can be broadcasted to the circuits through the common data line. The present invention also provides an architecture for implementing such method.

Abstract: A test method for a plurality of circuits respectively having inputs for greatly reducing the required test time and the control circuit complexity is provided. The method includes steps of providing a set of test patterns for detecting a characteristic of the circuits, providing a common data line, and electrically connecting the circuit inputs to the common data line so that the test pattern can be broadcasted to the circuits through the common data line. The present invention also provides an architecture for implementing such method.

Abstract: A new built-in self-test architecture for multiple memories in a chip is proposed in the present invention. In this architecture, all memories under test are tested in parallel using only one address generator. When the address generated from the address generator exceeds one memory's address space the memory is turned off by a BIST controller. Each word in each memory is tested by a scan-in/out method. That is, the D flip-flops in the input and output ports of each memory are connected in series and form two scan chains, respectively. Only one data input and one data output are required for the scan chains of each memory. The outputs of all scan chains are connected to a self checker for fault analysis in parallel. The address generator, data generator, self checker and the test controller are all built in a chip to satisfy the requirement of built-in self-testing.

Abstract: An apparatus for measuring the current of a CMOS circuit includes a reference current generator to generate a reference current, a first current mirror to mirror the reference current, a second current mirror to mirror the current consumed by the CMOS circuit, an inverter to compare the above two mirrored currents and generate a signal to indicate which current is larger, and a multiplexer to switch between the normal circuit operation mode and the test mode. By this apparatus, it is possible to measure rapidly and accurately whether the CMOS circuit consumes an abnormally large current, thereby determining whether the CMOS circuit contains defects. This apparatus is based on the current-mode approach, hence can provide a high speed signal processing capability and has lower sensitivity to parameter deviation caused by process or operating temperature variations. It also provides scaleable sensing resolutions and programmable current reference.

Abstract: A built-in intermediate voltage sensor for CMOS circuits comprises a linear inverter, a first voltage control switch, a second voltage control switch, and a buffer. The linear inverter has an input end connected with an input signal under test. The first voltage control switch has a control end and an input end which are connected respectively with the input end and an output end of the linear inverter. The second voltage control switch has a control end and an input end which are connected respectively with the output end and the input end of the linear inverter. The buffer has an input end connected with the output end of the first voltage control switch and the output end of the second voltage control switch. The buffer gives forth an output voltage having a first logic value when the input signal has a voltage value of logic "0" or logic "1".