Patents by Inventor Kuen-Shyi Tsay

Kuen-Shyi Tsay has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6391700
    Abstract: A pad oxide layer is formed on a substrate, wherein the thickness of the pad oxide layer is about greater than 250 Å. The alignment photo-resist layer is selectively patterned by a conventional lithography method to define the N-well region. The pad oxide layer is partially etched by using etch method with the alignment photo-resist pattern as a mask until the thickness of the pad oxide layer is about 100 Å to form an alignment mark. The N-type ion-implant is performed by the alignment photo-resist pattern as a mask to form an N-doped region in the substrate. Then, the alignment photo-resist pattern is removed. The P-well photo-resist is defined and formed on the pad oxide layer, then performing a P-type ion-implant through the pad oxide layer into the substrate by means of the P-well photo-resist as a mask to form a P-doped region. Then remove the P-well photo-resist and proceed with the drive-in process to form the N-well region and P-well region.
    Type: Grant
    Filed: October 17, 2000
    Date of Patent: May 21, 2002
    Assignee: United Microelectronics Corp.
    Inventor: Kuen-Shyi Tsay
  • Patent number: 6268271
    Abstract: A method for forming a plurality of buried layers inside a semiconductor device is disclosed. The method includes the following steps. Firstly, a semiconductor substrate is provided. Then, the first type p+-type ions are implanted into the semiconductor substrate to form the p+-type region under the surface of semiconductor substrate. The semiconductor substrate is etched to form a plurality of concave portions and a plurality of convex portions using the first photoresist. The n+-type ions are second implanted into the semiconductor substrate as a plurality of n+-type region. Next, the oxide layer is deposited over the surface of the plurality of concave portions and the surface of the plurality of convex portions. The plurality of n+-type regions are heated to form as the buried layers. The oxide layer is removed. Finally, a silicon layer is formed to fill the plurality of concave of portions a silicon layer and to cover the surface of the plurality of convex portions.
    Type: Grant
    Filed: May 31, 2000
    Date of Patent: July 31, 2001
    Assignee: United Microelectronics Corp.
    Inventor: Kuen-Shyi Tsay