Abstract: A phase locked loop (PLL) generates a phase locked signal and adjusts a frequency of the phase locked signal according to an incoming signal. The PLL includes an oscillator for generating the phased locked signal and a frequency detection module electrically coupled to the oscillator. The frequency detection module includes a pattern detector for detecting the two regular patterns in the incoming signal, a counter electrically coupled to the pattern detector for calculating the number of periods of the phase locked signal corresponding to the distance between the two regular patterns, and a comparator electrically coupled to the counter for comparing the number of periods with a predetermined value to generate a control signal, and using the control signal to control the oscillator to adjust the frequency of the phase locked loop signal.

Abstract: A sampling clock generator for BCA data decoding providing a sampling clock, which is proportional to the actual rotation speed of a disk. The sampling clock generator includes a frequency counter, a divider and a frequency divider. The frequency counter counts the number of pulses of a reference clock for each period of a rotation speed indicating signal of a spindle motor and generates a counting value. The divider divides the counting value by a predefined value and generates a divided value. The frequency divider is employed to generate the sampling clock. The frequency divider receives the reference clock and divides the frequency of the reference clock by the divided value to generate the sampling clock. The frequency divider also adjusts the phase of the sampling clock according to the BCA reproducing signal.

Abstract: A phase locked loop (PLL) generates a phase locked signal and adjusts a frequency of the phase locked signal according to an incoming signal. The PLL includes an oscillator for generating the phased locked signal and a frequency detection module electrically coupled to the oscillator. The frequency detection module includes a pattern detector for detecting the two regular patterns in the incoming signal, a counter electrically coupled to the pattern detector for calculating the number of periods of the phase locked signal corresponding to the distance between the two regular patterns, and a comparator electrically coupled to the counter for comparing the number of periods with a predetermined value to generate a control signal, and using the control signal to control the oscillator to adjust the frequency of the phase locked loop signal.

Abstract: An optical discriminating system is for discriminating whether a reflected light beam is from headers of an optical storage medium. Each header comprises a first embossed position and a second embossed position for recording an address information. A light beam detecting module is for receiving the reflected light beam. When the reflected light beam is from the first or second embossed position, a first or second header signal is generated. When the reflected light beam comprises the address information, an address mark signal is generated. A signal detecting module is for receiving the first header signal, the second header signal, and the address mark signal. When continuously receiving the first and second header signals, and also the address mark signal at the same time, then the signal detecting module discriminates that the reflected light beam is from one of the headers.

Abstract: A sampling clock generator for BCA data decoding providing a sampling clock, which is proportional to the actual rotation speed of a disk. The sampling clock generator includes a frequency counter, a divider and a frequency divider. The frequency counter counts the number of pulses of a reference clock for each period of a rotation speed indicating signal of a spindle motor and generates a counting value. The divider divides the counting value by a predefined value and generates a divided value. The frequency divider is employed to generate the sampling clock. The frequency divider receives the reference clock and divides the frequency of the reference clock by the divided value to generate the sampling clock. The frequency divider also adjusts the phase of the sampling clock according to the BCA reproducing signal.

Abstract: A circuit and method for protecting the run length in RLL (run length limited) code is proposed to correct the illegal run length in an EFM (eight to fourteen modulation) signal. The proposed circuit comprises a sampling unit for sampling a RF signal with a high frequency sampling clock, and generating a high frequency sampling signal. The frequency of the high frequency sampling clock is higher then the frequency of the EFM signal. A detector is employed to receive and to detect the high frequency sampling signal whether there is any illegal run length in the EFM signal, and to generate control signals. Two reference signal generators are employed to generate an ideal front reference signal and an ideal rear reference signal, respectively, corresponding to the control signals. A first difference generator and a second difference generator are employed to generate a first difference and a second difference according to the front and rear reference signals and the high frequency sampling signal, respectively.

Abstract: A circuit and method for protecting the run length in RLL (run length limited) code is proposed to correct the illegal run length in an EFM (eight to fourteen modulation) signal. The proposed circuit comprises a sampling unit for sampling a RF signal with a high frequency sampling clock, and generating a high frequency sampling signal. The frequency of the high frequency sampling clock is higher then the frequency of the EFM signal. A detector is employed to receive and to detect the high frequency sampling signal whether there is any illegal run length in the EFM signal, and to generate control signals. Two reference signal generators are employed to generate an ideal front reference signal and an ideal rear reference signal, respectively, corresponding to the control signals. A first difference generator and a second difference generator are employed to generate a first difference and a second difference according to the front and rear reference signals and the high frequency sampling signal, respectively.