Abstract: Embodiments of the present disclosure relate to a system and method for incremental compilation. The method includes identifying a change to a portion of a circuit design. The circuit design without the change was previously compiled to an FPGA. The method also includes configuring a transactor of the FPGA to simulate the portion of the circuit design with the change and configuring the FPGA to use the transactor to simulate the portion of the circuit design with the change.

Abstract: A method is presented for responding to user input by displaying when a circuit has a property expressed by an assertion based on data indicating values of signals of the circuit at a succession of times. The assertion expresses the property as a first sequence of expressions, and separately defines for each expression a corresponding evaluation time relative to the succession of times at which the expression is to be evaluated. The circuit has the property only if every expression of the first sequence evaluates true at its corresponding evaluation time. The method includes displaying a representation of each expression of the first sequence and identifying each variable that caused that expression to evaluate false and distinctively marking that variable's symbol relative to other variable symbols within the display for each expression of the first sequence that evaluates false at its corresponding evaluation time.

Abstract: User's register transfer level (RTL) design is analyzed and instrumented so that signals of interest are preserved and can be located in the netlist after synthesis. Then, the user's original flow of RTL synthesis and design partition is performed. The output is analyzed to locate the signals of interest. Latches are selectively inserted to the netlist to ensure that signal values can be accessed at runtime. After that, a place and route (P&R) process is performed, and the outputs are analyzed to correlate signal names to registers (flip-flops and latches) or memory blocks locations is field programmable gate array (FPGA) devices. A correlation database is built and kept for runtime use. During runtime, a software component may be provided on a workstation for the user to query signal values corresponding to RTL hierarchical signal names.

Abstract: A virtual platform simulates behavior of a modular circuit based on a circuit design including both high-level and low-level models of circuit modules. A compiler that converts the high-level and low-level models into executable models prior to an initial simulation also generates a separate “replay engine” corresponding to each low-level module for use during subsequent replay simulations. During the initial simulation, the virtual platform simulates circuit behavior by concurrently executing the high-level and low-level executable models and recording data representing behavior of output signals of the low-level design modules modeled by the executable models. To speed up subsequent replays of the simulation, the virtual platform executes one or more of the replay engines in lieu of executing their corresponding low-level executable models.

Abstract: User's register transfer level (RTL) design is analyzed and instrumented so that signals of interest are preserved and can be located in the netlist after synthesis. Then, the user's original flow of RTL synthesis and design partition is performed. The output is analyzed to locate the signals of interest. Latches are selectively inserted to the netlist to ensure that signal values can be accessed at runtime. After that, a place and route (P&R) process is performed, and the outputs are analyzed to correlate signal names to registers (flip-flops and latches) or memory blocks locations is field programmable gate array (FPGA) devices. A correlation database is built and kept for runtime use. During runtime, a software component may be provided on a workstation for the user to query signal values corresponding to RTL hierarchical signal names.

Abstract: User's register transfer level (RTL) design is analyzed and instrumented so that signals of interest are preserved and can be located in the netlist after synthesis. Then, the user's original flow of RTL synthesis and design partition is performed. The output is analyzed to locate the signals of interest. Latches are selectively inserted to the netlist to ensure that signal values can be accessed at runtime. After that, a place and route (P&R) process is performed, and the outputs are analyzed to correlate signal names to registers (flip-flops and latches) or memory blocks locations in field programmable gate array (FPGA) devices. A correlation database is built and kept for runtime use. During runtime, a software component may be provided on a workstation for the user to query signal values corresponding to RTL hierarchical signal names.

Abstract: A method is presented for responding to user input by displaying when a circuit has a property expressed by an assertion based on data indicating values of signals of the circuit at a succession of times. The assertion expresses the property as a first sequence of expressions, and separately defines for each expression a corresponding evaluation time relative to the succession of times at which the expression is to be evaluated. The circuit has the property only if every expression of the first sequence evaluates true at its corresponding evaluation time. The method includes displaying a representation of each expression of the first sequence and identifying each variable that caused that expression to evaluate false and distinctively marking that variable's symbol relative to other variable symbols within the display for each expression of the first sequence that evaluates false at its corresponding evaluation time.

Abstract: A computer processes simulation data indicating values of circuit signals as functions of simulation time to determine whether a circuit exhibits a property defined by an assertion. The assertion expresses the property as a sequence of expressions, each a function of one or more variables, where each variable represents a value of one or more signals or a value of another sequence of expressions. The assertion statement separately defines an evaluation time for each expression, a particular simulation time at which the expression is to be evaluated. Each expression must evaluate true if the circuit has the property. The computer produces a display including a representation of each expression of the property including a separate variable symbol for each of its variables. For each expression that evaluated false, the computer identifies each variable that caused that expression to evaluate false and distinctively marks that variable's symbol relative to other variable symbols within the display.

Abstract: User's RTL design is analyzed and instrumented so that signals of interest are preserved and can be located in the net list after synthesis. Then, the user's original flow of RTL synthesis and design partition is performed. The output is analyzed to locate the signals of interest. Latches are selectively inserted to the net list to ensure that signal values can be accessed at runtime. After that, a P&R process is performed, and the outputs are analyzed to correlate signal names to registers (flip-flops and latches) or memory blocks locations in FPGAs. A correlation database is built and kept for runtime use. During runtime, a software component may be provided on a workstation for the user to query signal values corresponding to RTL hierarchical signal names.

Abstract: A computer-based simulation process executes a checkpoint operation while simulating behavior of an electronic circuit by forking an active checkpoint process having the same state as the original simulation process. While simulation time for the simulation process continues to increase after executing the checkpoint operation, simulation time for the checkpoint process remains unchanged so that the checkpoint process remains in the state of the simulation at the simulation time it executed the checkpoint operation (the “checkpoint time”). When the checkpoint process subsequently receives a request to resume simulating the circuit, it forks a new simulation process that mimics the original simulation process as of checkpoint time, and the new simulation process then begins to advance its simulation time, thereby enabling it to re-simulate behavior of the electronic circuit previously simulated by the original simulation process starting from the checkpoint time.

Abstract: A virtual platform simulates behavior of a modular circuit based on a circuit design including both high-level and low-level models of circuit modules. A compiler that converts the high-level and low-level models into executable models prior to an initial simulation also generates a separate “replay engine” corresponding to each low-level module for use during subsequent replay simulations. During the initial simulation, the virtual platform simulates circuit behavior by concurrently executing the high-level and low-level executable models and recording data representing behavior of output signals of the low-level design modules modeled by the executable models. To speed up subsequent replays of the simulation, the virtual platform executes one or more of the replay engines in lieu of executing their corresponding low-level executable models.

Abstract: A computer-based simulation process executes a checkpoint operation while simulating behavior of an electronic circuit by forking an active checkpoint process having the same state as the original simulation process. While simulation time for the simulation process continues to increase after executing the checkpoint operation, simulation time for the checkpoint process remains unchanged so that the checkpoint process remains in the state of the simulation at the simulation time it executed the checkpoint operation (the “checkpoint time”). When the checkpoint process subsequently receives a request to resume simulating the circuit, it forks a new simulation process that mimics the original simulation process as of checkpoint time, and the new simulation process then begins to advance its simulation time, thereby enabling it to re-simulate behavior of the electronic circuit previously simulated by the original simulation process starting from the checkpoint time.

Abstract: A computer processes simulation data indicating values of circuit signals as functions of simulation time to determine whether a circuit exhibits a property defined by an assertion. The assertion expresses the property as a sequence of expressions, each a function of one or more variables, where each variable represents a value of one or more signals or a value of another sequence of expressions. The assertion statement separately defines an evaluation time for each expression, a particular simulation time at which the expression is to be evaluated. Each expression must evaluate true if the circuit has the property. The computer produces a display including a representation of each expression of the property including a separate variable symbol for each of its variables. For each expression that evaluated false, the computer identifies each variable that caused that expression to evaluate false and distinctively marks that variable's symbol relative to other variable symbols within the display.