Abstract: Various embodiments of the present application are directed towards an integrated chip. The integrated chip includes a first fin structure and a second fin structure disposed on a base region of a substrate. A first source/drain region is disposed on the first fin structure. A second source/drain region is disposed on the second fin structure. A gate structure overlies the base region of the substrate and is spaced laterally between the first and second fin structures. A bottom surface of the gate structure is disposed below bottoms of the first and second source/drain regions.

Abstract: Some embodiments relate to a memory cell, including: a write transistor on a substrate and comprising a first gate terminal, a first source/drain region, and a second source/drain region coupled to a storage node; a first read transistor on the substrate and comprising a second gate terminal coupled to the storage node and a gate dielectric with a first capacitance; and a capacitor spaced from the first read transistor and the write transistor and further separated from the substrate by the first read transistor and the write transistor, wherein the capacitor is coupled to the storage node and has a second capacitance that is over twice the first capacitance.

Abstract: The present disclosure relates to an integrated chip including a first metal layer over a substrate. A second metal layer is over the first metal layer. An ionic crystal layer is between the first metal layer and the second metal layer. A metal oxide layer is between the first metal layer and the second metal layer. The first metal layer, the second metal layer, the ionic crystal layer, and the metal oxide layer are over a transistor device that is arranged along the substrate.

Abstract: A neural network circuit includes an input neuron layer comprises a plurality of first neurons. A hidden neuron layer includes a plurality of second neurons, wherein each of the second neurons comprises a probabilistic bit having a time-varying resistance. The probabilistic bit is a magnetic tunnel junction structure comprises a pinned layer, a free layer, and a tunneling barrier layer between the pinned layer and the free layer. A weight matrix comprising a plurality of synapse units, each of the synapse units connecting one of the plurality of first neurons to a corresponding one of the plurality of first neurons.

Abstract: A device structure includes a first electrode overlying a substrate; a node dielectric contacting the first electrode and including a dielectric material having a dielectric constant greater than 30; and a second electrode contacting the node dielectric. A first one of the first electrode and the second electrode includes a first catalytic metal plate in direct contact with the node dielectric and having a first electronegativity that is not greater than an electronegativity of molybdenum.

Abstract: A method according to the present disclosure includes forming a bottom electrode layer over a substrate, forming an insulator layer over the bottom electrode layer, depositing a semiconductor layer over the bottom electrode layer, depositing a ferroelectric layer over the semiconductor layer, forming a top electrode layer over the ferroelectric layer, and patterning the bottom electrode layer, the insulator layer, the semiconductor layer, the ferroelectric layer, and the top electrode layer to form a memory stack. The semiconductor layer includes a plurality of portions with different thicknesses.

Abstract: In some embodiments, the present disclosure provides an integrated chip including a first electrode made of a metal; a second electrode disposed over the first electrode; a ferroelectric layer between the first and second electrodes; and an interfacial layer separating the ferroelectric layer and the first electrode, the interfacial layer comprising a semiconductor material and configured to space the first electrode from the ferroelectric layer.

Abstract: A semiconductor structure according to the present disclosure includes a conductive feature in a top portion of a substrate, a bottom electrode layer over and in electrical coupling with the conductive feature, an insulator layer over the bottom electrode layer, a semiconductor layer over the insulator layer, a ferroelectric layer over the semiconductor layer, and a top electrode layer over the ferroelectric layer. The semiconductor layer includes a plurality of portions with different thicknesses.

Abstract: Various embodiments of the present disclosure are directed towards a ferroelectric memory device comprising a chimney seed structure. A ferroelectric layer overlies a bottom electrode layer, and a top electrode layer overlies the ferroelectric layer. The top electrode layer, the ferroelectric layer, and the bottom electrode layer form a plurality of memory cells, and a dielectric wall extends through the top electrode layer and segments the top electrode layer into a plurality top electrodes individual to the memory cells. The chimney seed structure underlies the ferroelectric layer and extends through the bottom electrode layer from the ferroelectric layer. The chimney seed structure is configured to seed ferroelectric crystalline growth in the ferroelectric layer to allow the ferroelectric layer to achieve a large remanent polarization with a small thickness. The small thickness increases read speeds, while the large remanent polarization increases a read window and hence reliability.

Abstract: The present disclosure relates to an integrated chip including a first metal layer over a substrate. A second metal layer is over the first metal layer. An ionic crystal layer is between the first metal layer and the second metal layer. A metal oxide layer is between the first metal layer and the second metal layer. The first metal layer, the second metal layer, the ionic crystal layer, and the metal oxide layer are over a transistor device that is arranged along the substrate.

Abstract: A semiconductor structure may be located over a substrate, and may include a parallel connection of a first component and a second component. The first component includes a series connection of a diode and a capacitor that is selected from a metal-ferroelectric-metal capacitor and a metal-antiferroelectric-metal capacitor. The second component includes a battery structure. The semiconductor structure may be used as a combination of an energy harvesting device and an energy storage structure that utilizes heat from adjacent semiconductor devices or from other heat sources.

Abstract: A resistive random access memory (ReRAM) apparatus is provided. The ReRAM apparatus includes a plurality of memory cells, each of the memory cells comprises a transistor and a resistor; a bit line connected to a first terminal of the resistor of each of the memory cells; a local source line connected to a source electrode of the transistor of each of the memory cells; and a driving cell connected between the local source line and a global source line. A method for operating the ReRAM apparatus is also provided.

Abstract: A semiconductor die package includes an inductor-capacitor (LC) semiconductor die that is directly bonded with a logic semiconductor die. The LC semiconductor die includes inductors and capacitors that are integrated into a single die. The inductors and capacitors of the LC semiconductor die may be electrically connected with transistors and other logic components on the logic semiconductor die to form a voltage regulator circuit of the semiconductor die package. The integration of passive components (e.g., the inductors and capacitors) of the voltage regulator circuit into a single semiconductor die reduces signal propagation distances in the voltage regulator circuit, which may increase the operating efficiency of the voltage regulator circuit, may reduce the formfactor for the semiconductor die package, may reduce parasitic capacitance and/or may reduce parasitic inductance in the voltage regulator circuit (thereby improving the performance of the voltage regulator circuit), among other examples.

Abstract: An interfacial layer is formed in a manner that enables a ferroelectric layer to be formed such that formation of ferroelectric crystalline phases (e.g., orthorhombic crystalline phases) in the ferroelectric layer is increased and formation of non-ferroelectric crystalline phases (e.g., monoclinic phases, tetragonal phases) in the ferroelectric layer is reduced. To achieve this, the grain size and/or other properties of the interfacial layer may be controlled during formation of the interfacial layer such that the grain size and/or other properties of the interfacial layer facilitate formation of a larger grain size in the ferroelectric layer. At larger grain sizes in the ferroelectric layer, the concentration of the ferroelectric crystalline phases in the crystal structure of the ferroelectric layer may be increased relative to if the ferroelectric layer were formed to a smaller grain size.

Abstract: A semiconductor die package includes an inductor-capacitor (LC) semiconductor die that is directly bonded with a logic semiconductor die. The LC semiconductor die includes inductors and capacitors that are integrated into a single die. The inductors and capacitors of the LC semiconductor die may be electrically connected with transistors and other logic components on the logic semiconductor die to form a voltage regulator circuit of the semiconductor die package. The integration of passive components (e.g., the inductors and capacitors) of the voltage regulator circuit into a single semiconductor die reduces signal propagation distances in the voltage regulator circuit, which may increase the operating efficiency of the voltage regulator circuit, may reduce the formfactor for the semiconductor die package, may reduce parasitic capacitance and/or may reduce parasitic inductance in the voltage regulator circuit (thereby improving the performance of the voltage regulator circuit), among other examples.

Abstract: Provided are ferroelectric tunnel junction (FTJ) structures, memory devices, and methods for fabricating such structures and devices. An FTJ structure includes a first electrode, a ferroelectric material layer, and a catalytic metal layer in contact with the ferroelectric material layer.

Abstract: A semiconductor structure includes an inductive metal line located in a dielectric material layer that overlies a semiconductor substrate and laterally encloses a first area; and an array of first ferromagnetic plates including a first ferromagnetic material and overlying or underlying the inductive metal line. For any first point that is selected within volumes of the first ferromagnetic plates, a respective second point exists within a horizontal surface of the inductive metal line such that a line connecting the first point and the second point is vertical or has a respective first taper angle that is less than 20 degrees with respective to a vertical direction. The magnetic field passing through the first ferromagnetic plates is applied generally along a hard direction of magnetization and the hysteresis effect is minimized.

Abstract: A memory device includes a transistor device; a memory cell electrically coupled to a source or drain of the transistor device, wherein the memory cell includes an FJT structure; and a heating structure formed around the memory cell on a plurality of sides. The FJT structure includes a first conductive electrode having sidewalls that extend in a vertical direction to a first elevation level, a second conductive electrode having sidewalls that extend in the vertical direction to the first elevation level, and a switching barrier disposed between the first conductive electrode and the second conductive electrode and having sidewalls that extend in the vertical direction to the first elevation level, wherein the vertically extending sidewalls of the first conductive electrode, the second conductive electrode, and the switching barrier terminate at the first elevation level. The switching barrier includes ferroelectric (Fe) material that may be polarized to store information.

Abstract: A pyroelectric generator may be included in the same semiconductor device as a radio frequency (RF) switch (e.g., a phase-change material (PCM) RF switch and/or other types of RF switch). The pyroelectric generator includes a pyroelectric material layer between two electrodes. The pyroelectric generator is configured to scavenge thermal energy that is generated during the operation of the RF switch, and to convert the thermal energy into electrical energy that may be stored and reused.

Abstract: A semiconductor device includes a first capacitor having a ferroelectric film disposed between two electrodes, a second capacitor, having another dielectric film disposed between two electrodes. A first voltage is applied across the first capacitor such that the ferroelectric film is polarized, altering the effective resistance through the device. A second voltage is applied across the first capacitor, such that a leakage current transits the ferroelectric film, and accumulates along an electrode of the second capacitor, and the gate of a transistor, thereby effecting a change to the drain to source resistance of the transistor which may be measured to determine the polarization state of the ferroelectric film.