Patents by Inventor Kug-Hwan Kim

Kug-Hwan Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10770560
    Abstract: A semiconductor device according to an example embodiment of the present inventive concept includes a substrate having a first region and a second region horizontally separate from the first region; a first gate line in the first region, the first gate line including a first lower work function layer and a first upper work function layer disposed on the first lower work function layer; and a second gate line including a second lower work function layer in the second region, the second gate line having a width in a first, horizontal direction equal to or narrower than a width of the first gate line in the first direction, wherein an uppermost end of the first upper work function layer and an uppermost end of the second lower work function layer are each located at a vertical level higher than an uppermost end of the first lower work function layer with respect to a second direction perpendicular to the first direction.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: September 8, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jeong Hyuk Yim, Kug Hwan Kim, Wan Don Kim, Jung Min Park, Jong Ho Park, Byoung Hoon Lee, Yong Ho Ha, Sang Jin Hyun, Hye Ri Hong
  • Publication number: 20190355825
    Abstract: A semiconductor device according to an example embodiment of the present inventive concept includes a substrate having a first region and a second region horizontally separate from the first region; a first gate line in the first region, the first gate line including a first lower work function layer and a first upper work function layer disposed on the first lower work function layer; and a second gate line including a second lower work function layer in the second region, the second gate line having a width in a first, horizontal direction equal to or narrower than a width of the first gate line in the first direction, wherein an uppermost end of the first upper work function layer and an uppermost end of the second lower work function layer are each located at a vertical level higher than an uppermost end of the first lower work function layer with respect to a second direction perpendicular to the first direction.
    Type: Application
    Filed: December 10, 2018
    Publication date: November 21, 2019
    Inventors: Jeong Hyuk YIM, Kug Hwan KIM, Wan Don KIM, Jung Min PARK, Jong Ho PARK, Byoung Hoon LEE, Yong Ho HA, Sang Jin HYUN, Hye Ri HONG
  • Patent number: 9640443
    Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate including first through fourth areas. Moreover, first through fourth gate insulating layers are on the first through fourth areas, respectively. Amounts of work function control materials in the first through fourth gate insulating layers, nitrogen concentrations in the first through fourth gate insulating layers, and/or thicknesses of the first through fourth gate insulating layers vary among the first through fourth gate insulating layers. Methods for fabricating semiconductor devices are also provided.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: May 2, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kug-Hwan Kim, Jong-Ho Lee, Woo-Hee Kim, Nae-In Lee
  • Publication number: 20160276225
    Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate including first through fourth areas. Moreover, first through fourth gate insulating layers are on the first through fourth areas, respectively. Amounts of work function control materials in the first through fourth gate insulating layers, nitrogen concentrations in the first through fourth gate insulating layers, and/or thicknesses of the first through fourth gate insulating layers vary among the first through fourth gate insulating layers. Methods for fabricating semiconductor devices are also provided.
    Type: Application
    Filed: May 13, 2016
    Publication date: September 22, 2016
    Inventors: Kug-Hwan Kim, Jong-Ho Lee, Woo-Hee Kim, Nae-In Lee
  • Patent number: 9177865
    Abstract: Provided are methods for fabricating a semiconductor device. A gate dielectric layer is formed on a substrate including first through third regions. A first functional layer is formed on only the first region of the first through third regions. A second functional layer is formed on only the first and second regions of the first through third regions. A threshold voltage adjustment layer is formed on the first through third regions. The threshold voltage adjustment layer includes a work function adjustment material. The work function adjustment material is diffused into the gate dielectric layer by performing a heat treatment process with respect to the substrate.
    Type: Grant
    Filed: May 7, 2014
    Date of Patent: November 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo-Hee Kim, Nae-In Lee, Kug-Hwan Kim, Jong-Ho Lee
  • Publication number: 20150187763
    Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate including first through fourth areas. Moreover, first through fourth gate insulating layers are on the first through fourth areas, respectively. Amounts of work function control materials in the first through fourth gate insulating layers, nitrogen concentrations in the first through fourth gate insulating layers, and/or thicknesses of the first through fourth gate insulating layers vary among the first through fourth gate insulating layers. Methods for fabricating semiconductor devices are also provided.
    Type: Application
    Filed: September 18, 2014
    Publication date: July 2, 2015
    Inventors: Kug-Hwan Kim, Jong-Ho Lee, Woo-Hee Kim, Nae-In Lee
  • Publication number: 20140363960
    Abstract: Provided are methods for fabricating a semiconductor device. A gate dielectric layer is formed on a substrate including first through third regions. A first functional layer is formed on only the first region of the first through third regions. A second functional layer is formed on only the first and second regions of the first through third regions. A threshold voltage adjustment layer is formed on the first through third regions. The threshold voltage adjustment layer includes a work function adjustment material. The work function adjustment material is diffused into the gate dielectric layer by performing a heat treatment process with respect to the substrate.
    Type: Application
    Filed: May 7, 2014
    Publication date: December 11, 2014
    Inventors: Woo-Hee Kim, Nae-In Lee, Kug-Hwan Kim, Jong-Ho Lee