Abstract: The present application provides an air purification device and a control method. The air purification device includes a frame body, wherein one side of the frame body is provided with an air inlet and the other side is provided with an air outlet, and the frame body is used for accommodating a micro-electrostatic module and a charging mechanism; the micro-electrostatic module comprising a filter element, wherein the filter element comprises a plurality of air channels for air circulation, and the filter element is arranged near the air outlet; and the charging mechanism is located at one side of the filter element far from the air outlet, and comprising a plurality of electrode heads distributed on the surface of the filter element, so that the discharge area of the charging mechanism covers the whole filter element.

Abstract: An electrostatic charging device and an assembly method thereof, the electrostatic charging device includes a frame body, at least one first accommodating groove arranged inside the frame body, an electrode body arranged inside the at least one first accommodating groove and arranged along a length direction of the at least one first accommodating groove, and a plurality of electrode heads penetrating through a wall of the at least one first accommodating groove and connected with the electrode body; the plurality of electrode heads are arranged along the electrode body at intervals, such that a discharging area covers a whole of an interior of the frame body; the electrode body and a connector configured to connect the plurality of electrode heads and the electrode body are both sealed in the at least one first accommodating groove.

Abstract: The present invention relates to a vortex electric field purification device and a design method therefor, belonging to the technical field of air purification. The vortex electric field purification device includes a frame, where a dust collection area and an ionization area are arranged inside the frame in parallel, both the dust collection area and the ionization area include a plurality of polar plates parallel to each other and arranged at intervals, the first direction is parallel to a direction from an air inlet side of the purification device to a leeward side of the purification device, and the second direction is perpendicular to the first direction. The vortex electric field purification device can avoid the phenomenon of ignition or arcing of the ionization area and the dust collection area, has high reliability, and is economical and durable.

Abstract: The present invention relates to an ion box compatible with direct-current power supply and vortex power supply, and a purification device, belonging to the technical field of air purification. The ion box includes a frame, where a dust collection area and an ionization area are arranged inside the frame in parallel, both the dust collection area and the ionization area include a plurality of polar plates parallel to each other and arranged at intervals, a distance between adjacent low-voltage polar plates or adjacent high-voltage polar plates located in the ionization area is 44-58 mm, a distance between adjacent low-voltage polar plates located in the dust collection area is 11-16 mm, an ionization electric field is formed inside the ionization area. According to the present invention, the technical problem in the prior art that the purification efficiency is affected by frequent cleaning and maintenance of the purification device can be solved.

Abstract: A modular connector system with components that can be economically assembled to provide reliable high signal integrity in a harsh environment (e.g., automobile). A connector includes a subassembly disposed in a cavity of a housing. The connector has features configured to restrain movements within the subassembly and/or between the subassembly and housing, which would otherwise be problematic due to the harsh environment. The subassembly includes a subassembly housing, a terminal disposed therein, and first and second shields partially stacked. The stacked portion of the first shield includes a stop device protruding toward the subassembly housing through a slot of the second shield, and/or a position limiting device protruding away from the subassembly housing to engage a stop device of the housing. The housing includes a beam with a distal end engaging the first shield. The connector includes a CCPA having a stop device abutting both the first and second shields.

Abstract: A modular connector system with components that can be economically assembled to both provide high signal integrity and supply reliable power in a harsh environment, such as an automobile. A connector includes a housing having a mating end, a back end, cavities extending from the mating end toward the back end, and latches extending inside the housing and having distal ends toward the back end. Signal and power terminal assemblies are disposed in respective cavities and engage respective latches. A signal terminal assembly includes a signal terminal, a signal cable attached to the signal terminal, and a shield substantially encircling the signal terminal and cable attachment. A power terminal assembly includes an insulative holder, a power terminal held in the insulative holder, and a power cable attached to the power terminal. Other disclosed techniques enable signal and power terminal assemblies stably and interchangeably disposed in the cavities.

Abstract: A method of decoding a codeword that satisfies a k constraint into output data includes, using a decoder of a hard disk drive system, converting each bit of the codeword in Non-Return-to-Zero format, extracting, from the converted codeword, a plurality of data blocks comprising a first data block and a plurality of remaining data blocks, performing a first analysis on the plurality of data blocks for modifying each of the plurality of data blocks that satisfies a first predetermined criterion, and performing a second analysis on the plurality of data blocks after the first analysis for modifying each of the plurality of data blocks that satisfies a second predetermined criterion to obtain the output data.

Abstract: An adaptation technique for decoding low-density parity-check (LDPC) codes for hard disk drive (HDDs) systems is disclosed. The method includes tuning the normalization factor for LDPC decoding for each data zone and read head during the test stage of manufacturing. The LDPC decoder can be either a sum-product algorithm (SPA) decoder or a Min-Sum decoder. The channel detector can be any soft-output detector, such as a soft-output Viterbit detector (SOVA), a BCJR detector, a pattern-dependent noise-predictive (PDNP) detector, or a bi-directional pattern-dependent noise-predictive (BiPDNP) detector. The adaptation technique can optimize the LDPC decoding performance for each data zone and read head, thereby relaxing the acceptance criteria for hard disk drive read/write heads and disk media, enabling acceptance and use of a much broader range of head and media for hard disk drives.

Abstract: A method of decoding a codeword that satisfies a k constraint into output data includes, using a decoder of a hard disk drive system, converting each bit of the codeword in Non-Return-to-Zero format, extracting, from the converted codeword, a plurality of data blocks comprising a first data block and a plurality of remaining data blocks, performing a first analysis on the plurality of data blocks for modifying each of the plurality of data blocks that satisfies a first predetermined criterion, and performing a second analysis on the plurality of data blocks after the first analysis for modifying each of the plurality of data blocks that satisfies a second predetermined criterion to obtain the output data.

Abstract: There is provided an error correction method for a non-volatile memory. The method includes receiving a codeword read from the non-volatile memory, computing a reliability information for each bit of the codeword received, and performing a reduced-complexity soft-decision decoding (SDD) technique to decode the received codeword. In particular, the SDD technique includes forming a set of test patterns based on the reliability data, and determining whether to perform a HDD of a test pattern in the set of test patterns based on a distance between the test pattern and a candidate pattern. There is also provided an error correction module for a non-volatile memory and a memory system incorporating the error correction module.

Abstract: A method of encoding an input data into a codeword that satisfy a k constraint includes partitioning the input data into a plurality of data blocks comprising a first data block and a plurality of remaining data blocks; performing a first analysis of the plurality of data blocks for modifying each of the plurality of remaining data blocks that satisfy a first predetermined criterion; performing a second analysis of the plurality of data blocks after the first analysis for modifying each of the plurality of data blocks that satisfy a second predetermined criterion; and converting each bit of the plurality of data blocks after the second analysis to produce the codeword in Non-Return-to-Zero (NRZ) format with the k constraint. There is also provided a method of decoding the codeword with satisfies the k constraint into an output data, and the corresponding encoder and decoder.

Abstract: According to an embodiment of the present invention, a data storage device comprising a motor having a stator is disclosed. The stator may include a substrate having a first surface and a second surface opposite to the first surface; and a n-phase winding arrangement having n phase windings; wherein each phase winding comprises m flat fractional-pitch coils arranged on the first surface of the substrate such that the coils are spaced apart uniformly along a closed loop and connected in series; wherein each coil together with an angular section of the substrate between the coil and an adjacent coil of the same phase winding defines a stator pole-pair; and wherein m is an integer larger than 1.

Abstract: A method of encoding an input data into a codeword that satisfy a k constraint includes partitioning the input data into a plurality of data blocks comprising a first data block and a plurality of remaining data blocks; performing a first analysis of the plurality of data blocks for modifying each of the plurality of remaining data blocks that satisfy a first predetermined criterion; performing a second analysis of the plurality of data blocks after the first analysis for modifying each of the plurality of data blocks that satisfy a second predetermined criterion; and converting each bit of the plurality of data blocks after the second analysis to produce the codeword in Non-Return-to-Zero (NRZ) format with the k constraint. There is also provided a method of decoding the codeword with satisfies the k constraint into an output data, and the corresponding encoder and decoder.

Abstract: There is provided an error correction method for a non-volatile memory. The method includes receiving a codeword read from the non-volatile memory, computing a reliability information for each bit of the codeword received, and performing a reduced-complexity soft-decision decoding (SDD) technique to decode the received codeword. In particular, the SDD technique includes forming a set of test patterns based on the reliability data, and determining whether to perform a HDD of a test pattern in the set of test patterns based on a distance between the test pattern and a candidate pattern. There is also provided an error correction module for a non-volatile memory and a memory system incorporating the error correction module.

Abstract: According to an embodiment of the present invention, a data storage device comprising a motor having a stator is disclosed. The stator may include a substrate having a first surface and a second surface opposite to the first surface; and a n-phase winding arrangement having n phase windings; wherein each phase winding comprises m flat fractional-pitch coils arranged on the first surface of the substrate such that the coils are spaced apart uniformly along a closed loop and connected in series; wherein each coil together with an angular section of the substrate between the coil and an adjacent coil of the same phase winding defines a stator pole-pair; and wherein m is an integer larger than 1.

Abstract: An adaptation technique for decoding low-density parity-check (LDPC) codes for hard disk drive (HDDs) systems is disclosed. The method includes tuning the normalization factor for LDPC decoding for each data zone and read head during the test stage of manufacturing. The LDPC decoder can be either a sum-product algorithm (SPA) decoder or a Min-Sum decoder. The channel detector can be any soft-output detector, such as a soft-output Viterbit detector (SOVA), a BCJR detector, a pattern-dependent noise-predictive (PDNP) detector, or a bi-directional pattern-dependent noise-predictive (BiPDNP) detector. The adaptation technique can optimize the LDPC decoding performance for each data zone and read head, thereby relaxing the acceptance criteria for hard disk drive read/write heads and disk media, enabling acceptance and use of a much broader range of head and media for hard disk drives.

Abstract: According to embodiments of the present invention, a memory device with soft decision decoding is provided. The memory device includes a memory cell configured to store an input data bit; a memory sensor configured to read out a parameter associated with a state of the memory cell; a detector configured to determine, based on the parameter read out from the memory cell, a soft information indicating the likelihood that the input data bit stored in the memory cell is a “0” or the likelihood that the input data bit stored in the memory cell is a “1”; and a decoder configured to generate a decoded bit based on the soft information. Further embodiments relate to a method of performing soft-decision decoding on a data bit stored in a memory cell of a memory device.

Abstract: A method performed by a disk drive, comprising: receiving a plurality of signal samples over a channel in the disk drive; executing a forward pattern-dependent noise prediction (PDNP) operation on the plurality of the signal samples; generating, based on execution of the forward PDNP operation, a first detection of recorded data bits in the plurality of received signal samples; executing a backward PDNP operation on the plurality of the received signal samples; generating, based on execution of the backward PDNP operation, a second detection of recorded data bits in the plurality of received signal samples; comparing the first detection to the second detection; identifying, based on comparing, one or more erasures in the received plurality of signal samples; and generating one or more sequences of bits that promote correction of the one or more erasures.

Abstract: A method and system for encoding a segment of user data words into a segment of code words so that both modulation constraints and a predetermined parity-check constraint are satisfied. Each segment of the user data is partitioned into several data words, and encoded separately by first and second types of component code, which are referred to as the normal constrained code and the parity-related constrained code, respectively. The parity-check constraint over the combined code word is achieved by concatenating the sequence of normal constrained code words with a specific parity-related constrained code word chosen from a candidate code word set. Both the component codes are finite-state constrained codes, which are designed to have rates close to the Shannon capacity. Furthermore, they are based on the same finite state machine (FSM), which enables them to be connected seamlessly, without violating the modulation constraints.

Abstract: A method and system for encoding a segment of user data words into a segment of code words so that both modulation constraints and a predetermined parity-check constraint are satisfied. Each segment of the user data is partitioned into several data words, and encoded separately by first and second types of component code, which are referred to as the normal constrained code and the parity-related constrained code, respectively. The parity-check constraint over the combined code word is achieved by concatenating the sequence of normal constrained code words with a specific parity-related constrained code word chosen from a candidate code word set. Both the component codes are finite-state constrained codes, which are designed to have rates close to the Shannon capacity. Furthermore, they are based on the same finite state machine (FSM), which enables them to be connected seamlessly, without violating the modulation constraints.