Abstract: A lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS), including: a trench gate including a lower part inside a trench and an upper part outside the trench, a length of the lower part in a width direction of a conducting channel being less than that of the upper part, and the lower part extending into a body region and having a depth less than that of the body region; an insulation structure arranged between a drain region and the trench gate and extending downwards into a drift region, a depth of the insulation structure being less than that of the drift region.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method therefor. The semiconductor device includes: a base, where a first surface of the base is provided with a first trench and a second trench; a gate, provided in the first trench; a gate insulation isolation structure, provided in the first trench, wherein the gate insulation isolation structure covers the gate at a bottom, sides and a top of the gate; a source doped region, provided in the base, on both sides of the first trench and on both sides of the second trench; a trench conductive structure, provided in the second trench; a source electrode, provided on the trench conductive structure and the source doped region, and electrically connected to the trench conductive structure and the source doped region; and a drain electrode, provided on a second surface of the base.

Abstract: A semiconductor device comprises a drift region (100), a body region (110), a first doped region (111) and a second doped region (112)); a first trench penetrates the first doped region (111), the body region (110) extends into the drift region (100); an extension region (150) having an opposite conductivity type to the drift region (100) and surrounding the bottom wall of the first trench; where the first trench is filled with a first conductive structure (141) and a second conductive structure (142); a dielectric layer (130) formed between the second conductive structure (142) and the inner wall of the first trench, as well as between the first conductive structure (141) and the inner wall of the first trench; a second trench penetrating the first doped region (111) and the body region (110), and a dielectric layer (130) located between the third conductive structure (143) and the second trench (122).

Abstract: A preparation method for semiconductor device, comprising: forming a body region (110) in the drift region (100), forming a first doped region (111) and a second doped region (112) in the body region (110); forming a first trench (171) penetrating the first doped region (111) and the body region (110) and extending to the drift region (100); forming an extension region (150) with a conductivity type opposite to that of the drift region (100) and surrounding the bottom wall of the first trench (171); filling the first trench (171) with a dielectric layer (130) formed on the sidewall of the trench, a first conductive structure (141) located at the bottom of the trench and a second conductive structure (142) located at the top of the trench; forming a second trench (172) penetrating the body region (110) and extending into the drift region (100); filling the second trench (172) with a third conductive structure (143) and a dielectric layer (130) formed on the inner wall of the trench.

Abstract: The present application discloses a method and apparatus for processing a notification trigger message, which method and apparatus relate to the technical field of computers. One specific implementation of the method comprises: receiving a notification trigger message formed by triggering a notification, wherein the notification trigger message includes an identifier of a current push message corresponding to the notification; determining whether the identifier of the current push message exists in a message cache, and if the identifier of the current push message exists in a message cache, ignoring the notification trigger message, wherein the message cache is used for storing an identifier of a push message corresponding to a notification that has been responded to. The implementation can avoid multiple responses of a client to an identical notification.

Abstract: A semiconductor device comprises a drift region (100), a body region (110), a first doped region (111) and a second doped region (112)); a first trench penetrates the first doped region (111), the body region (110) extends into the drift region (100); an extension region (150) having an opposite conductivity type to the drift region (100) and surrounding the bottom wall of the first trench; where the first trench is filled with a first conductive structure (141) and a second conductive structure (142); a dielectric layer (130) formed between the second conductive structure (142) and the inner wall of the first trench, as well as between the first conductive structure (141) and the inner wall of the first trench; a second trench penetrating the first doped region (111) and the body region (110), and a dielectric layer (130) located between the third conductive structure (143) and the second trench (122).

Abstract: A preparation method for semiconductor device, comprising: forming a body region (110) in the drift region (100), forming a first doped region (111) and a second doped region (112) in the body region (110); forming a first trench (171) penetrating the first doped region (111) and the body region (110) and extending to the drift region (100); forming an extension region (150) with a conductivity type opposite to that of the drift region (100) and surrounding the bottom wall of the first trench (171); filling the first trench (171) with a dielectric layer (130) formed on the sidewall of the trench, a first conductive structure (141) located at the bottom of the trench and a second conductive structure (142) located at the top of the trench; forming a second trench (172) penetrating the body region (110) and extending into the drift region (100); filling the second trench (172) with a third conductive structure (143) and a dielectric layer (130) formed on the inner wall of the trench.

Abstract: A lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS), including: a trench gate including a lower part inside a trench and an upper part outside the trench, a length of the lower part in a width direction of a conducting channel being less than that of the upper part, and the lower part extending into a body region and having a depth less than that of the body region; an insulation structure arranged between a drain region and the trench gate and extending downwards into a drift region, a depth of the insulation structure being less than that of the drift region.

Abstract: A gallium nitride power device, including: a gallium nitride substrate; cathodes; a plurality of gallium nitride protruding structures arranged on the gallium nitride substrate and between the cathodes, a groove is formed between adjacent gallium nitride protruding structures; an electron transport layer, covering a top portion and side surfaces of each of the gallium nitride protruding structures; a gallium nitride layer, arranged on the electron transport layer and filling each of the grooves; a plurality of second conductivity type regions, where each of the second conductivity type regions extends downward from a top portion of the gallium nitride layer into one of the grooves, and the top portion of each of the gallium nitride protruding structures is higher than a bottom portion of each of the second conductivity type regions; and an anode, arranged on the gallium nitride layer and the second conductivity type regions.

Abstract: The present disclosure provides a method of manufacturing a surface nanotube array of a laser-melted stainless steel, including a step of an anodic oxidation treatment on the stainless steel, which includes performing the anodic oxidation treatment on the stainless steel by applying a voltage between the stainless steel as an anode and a graphite as a cathode in a solution formed by using sodium dihydrogen phosphate, perchloric acid, and ethylene glycol as a solute, and deionized water as a solvent.

Abstract: A gallium nitride power device, including: a gallium nitride substrate; cathodes; a plurality of gallium nitride protruding structures arranged on the gallium nitride substrate and between the cathodes, a groove is formed between adjacent gallium nitride protruding structures; an electron transport layer, covering a top portion and side surfaces of each of the gallium nitride protruding structures; a gallium nitride layer, arranged on the electron transport layer and filling each of the grooves; a plurality of second conductivity type regions, where each of the second conductivity type regions extends downward from a top portion of the gallium nitride layer into one of the grooves, and the top portion of each of the gallium nitride protruding structures is higher than a bottom portion of each of the second conductivity type regions; and an anode, arranged on the gallium nitride layer and the second conductivity type regions.

Abstract: The present disclosure provides a method of manufacturing a surface nanotube array of a laser-melted stainless steel, including a step of an anodic oxidation treatment on the stainless steel, which includes performing the anodic oxidation treatment on the stainless steel by applying a voltage between the stainless steel as an anode and a graphite as a cathode in a solution formed by using sodium dihydrogen phosphate, perchloric acid, and ethylene glycol as a solute, and deionized water as a solvent.

Abstract: A power semiconductor device includes a substrate; drain metal; a drift region; a base region; a gate structure; a first conductive type doped region contacting the base region on the side of the base region distant from the gate structure; a source region provided in the base region and between the first conductive type doped region and the gate structure; contact metal that is provided on the first conductive type doped region and forms a contact barrier having rectifying characteristics together with the first conductive type doped region below; and source metal wrapping the contact metal and contacting the source region.

Abstract: A heterojunction semiconductor device with a low on-resistance includes a metal drain electrode, a substrate, and a buffer layer. A current blocking layer arranged in the buffer layer, a gate structure is arranged on the buffer layer, and the gate structure comprises a metal gate electrode, GaN pillars and AlGaN layers, wherein a metal source electrode is arranged above the metal gate electrode; and the current blocking layer comprises multiple levels of current blocking layers, the centers of symmetry of the layers are collinear, and annular inner openings of the current blocking layers at all levels gradually become smaller from top to bottom. The AlGaN layers and the GaN pillars are distributed in a honeycomb above the buffer layer.

Abstract: Disclosed is a semiconductor device having an electrostatic discharge protection structure. The electrostatic discharge protection structure is a diode connected between a gate electrode and a source electrode of the semiconductor device. The diode comprises a diode body and two connection portions connected to two ends of the diode body and respectively used for electrically connecting to the gate electrode and the source electrode. Lower parts of the two connection portions are respectively provided with a trench. An insulation layer is provided on an inner surface of the trench and the surface of a substrate between trenches. The diode body is provided on the insulation layer on the surface of the substrate. The connection portions respectively extend downwards into respective trenches from one end of the diode body. A dielectric layer is provided on the diode, and a metal conductor layer is provided on the dielectric layer.

Abstract: Disclosed is a semiconductor device having an e1ectrostatic discharge protection structure. The e1ectrostatic discharge protection structure is a diode connected between a gate e1ectrode and a source e1ectrode of the semiconductor device. The diode comprises a diode body and two connection portions connected to two ends of the diode body and respectively used for electrically connecting to the gate e1ectrode and the source e1ectrode. Lower parts of the two connection portions are respective1y provided with a trench. An insulation 1ayer is provided on an inner surface of the trench and the surface of a substrate between trenches. The diode body is provided on the insu1ation 1ayer on the surface of the substrate. The connection portions respectively extend downwards into respective trenches from one end of the diode body. A dielectric layer is provided on the diode, and a meta1 conductor 1ayer is provided on the dielectric layer.

Abstract: This disclosure relates to a preparation method of a low-pH controlled-release intelligent corrosion inhibitor. The low-pH controlled-release intelligent corrosion inhibitor comprises a hydrogel with low pH responsiveness and a corrosion inhibiting substance having the capacity of corrosion inhibition. That is, a corrosion inhibiting substance is wrapped in a low-pH sensitive hydrogel. The swelling degree of the pH sensitive hydrogel may be changed according to the amounts of monomers and crosslinking agents so as to control the releasing speed of the corrosion inhibiting substance. By the soaking experiment and the measurements of electrochemical polarization curves and alternating impedance spectra, the sensitive and long-lasting features of the low-pH controlled-release intelligent corrosion inhibitor are indicated.

Abstract: This disclosure relates to a preparation method of a low-pH controlled-release intelligent corrosion inhibitor. The low-pH controlled-release intelligent corrosion inhibitor comprises a hydrogel with low pH responsiveness and a corrosion inhibiting substance having the capacity of corrosion inhibition. That is, a corrosion inhibiting substance is wrapped in a low-pH sensitive hydrogel. The swelling degree of the pH sensitive hydrogel may be changed according to the amounts of monomers and crosslinking agents so as to control the releasing speed of the corrosion inhibiting substance. By the soaking experiment and the measurements of electrochemical polarization curves and alternating impedance spectra, the sensitive and long-lasting features of the low-pH controlled-release intelligent corrosion inhibitor are indicated.