Abstract: A method for fabricating a semiconductor device, which improves the threshold voltage by forming an air tunnel in the lower part of the transistor channel of a semiconductor device, and also improves the short channel effect by making better the sub-threshold voltage properties and increasing the internal pressure between the drain and the source, as well as improving the ESD (electrostatic discharge) property.

Abstract: A method for fabricating a semiconductor device, which improves the threshold voltage by forming an air tunnel in the lower part of the transistor channel of a semiconductor device, and also improves the short channel effect by making better the sub-threshold voltage properties and increasing the internal pressure between the drain and the source, as well as improving the ESD (electrostatic discharge) property.

Abstract: A method for forming a gate electrode for a MOS type transistor including formation of an insulating layer on a portion of a semiconductor substrate is not used for the gate electrode. A spacer is formed on the sides of the insulating layer and a gate oxide and gate electrode layers are stacked on the portion of the semiconductor substrate that is used for forming the gate. Source/drain regions are formed by implanting ions after removing the insulating layer. A plug poly is formed in the opening portion left by the removal of the insulating layer. The spacer is then removed to allow LDD ion implantation true openings left by removal of the spacer. Prior to the LDD ion implantation, however, rapid thermal annealing is performed to activate the source/drain regions and the gate electrode, thereby effecting formation of a short effective channel of the gate, which is advantageous in high density integrated circuits.

Abstract: There is disclosed a method of manufacturing a semiconductor device capable of preventing two electrodes from being short.