Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. A support layer and a mold layer are partially etched off from the substrate, to form a mold pattern and a support pattern on the substrate such that a contact hole is formed through the support pattern and the mold pattern and an interconnector is exposed therethrough. A lower electrode layer is formed on the mask pattern to fill the contact hole, and a lower electrode is formed in the contact hole by partially removing the lower electrode layer and the mask pattern. The lower electrode is contact with the interconnector and is supported by the support pattern having the same thickness as the support layer.

Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. A support layer and a mold layer are partially etched off from the substrate, to form a mold pattern and a support pattern on the substrate such that a contact hole is formed through the support pattern and the mold pattern and an interconnector is exposed therethrough. A lower electrode layer is formed on the mask pattern to fill the contact hole, and a lower electrode is formed in the contact hole by partially removing the lower electrode layer and the mask pattern. The lower electrode is contact with the interconnector and is supported by the support pattern having the same thickness as the support layer.

Abstract: A semiconductor device including at least one first capacitor and at least one second capacitor. The at least one first capacitor includes a first storage node having a cylindrical shape. The at least one second capacitor includes a lower second storage node having a hollow pillar shape including a hollow portion, and an upper second storage node having a cylindrical shape and extending upward from the lower second storage node.

Abstract: A semiconductor device includes a lower electrode, a supporting member enclosing at least an upper portion of the lower electrode, a dielectric layer on the lower electrode and the supporting member, and an upper electrode disposed on the dielectric layer. The supporting member may have a first portion that extends over an upper part of the sidewall of the lower electrode, and a second portion covering the upper surface of the lower electrode. The first portion of the supporting member protrudes above the lower electrode.

Abstract: A semiconductor device includes a lower electrode, a supporting member enclosing at least an upper portion of the lower electrode, a dielectric layer on the lower electrode and the supporting member, and an upper electrode disposed on the dielectric layer. The supporting member may have a first portion that extends over an upper part of the sidewall of the lower electrode, and a second portion covering the upper surface of the lower electrode. The first portion of the supporting member protrudes above the lower electrode.

Abstract: In a method of forming a contact structure, first and second conductive structures may be formed on a lower structure to be spaced from each other. An insulating layer may be formed on the lower structure to cover the first and second conductive structures. A first hole exposing the first conductive structure may be formed through the insulating layer. A spacer may be formed on a sidewall of the first hole. A first contact electrically coupled to the first conductive structure may be formed in the first hole having the sidewall on which the spacer is formed. A portion of the insulating layer located between the spacers may be removed to form a second hole exposing the second conductive structure. A second contact electrically coupled to the second conductive structure may be formed in the second hole.

Abstract: A method of manufacturing a semiconductor device may involve providing a first insulation pattern on a substrate including first and second regions. The first insulation pattern may include a first contact hole for exposing the first region. A spacer may be provided on a sidewall of the first insulation pattern. A conductive pattern may be provided in the first contact hole such that a top surface of the conductive pattern is lower than a top surface of the first insulation pattern. A second insulation pattern may be provided on the conductive pattern. The first insulation pattern may be etched using the second insulation pattern and the spacer as a self-aligning mask to form a second contact hole for exposing the second region. A wiring may be provided in the second contact hole.

Abstract: In a method of forming a conductive pattern in a semiconductor device, a conductive layer including a metal is formed on a substrate. A mask including carbon is provided on the conductive layer, and the conductive pattern is formed on the substrate by etching the conductive layer using the mask as an etching mask. The mask is removed from the conductive pattern by an oxygen plasma ashing process. An oxidized portion of the conductive pattern is reduced. The conductive pattern may have a desired resistance by reducing the oxidized portion to improve electrical characteristics and reliability of the semiconductor device.

Abstract: An exemplary semiconductor device includes a semiconductor substrate on which lower electrodes are formed. The lower electrodes are arranged in an array including a rows extending substantially parallel to one another along a first direction. A stripe-shaped capacitor support pad is interposed between a pair of adjacent ones of the rows and is connected to lower electrodes in the pair of adjacent ones of the rows. The semiconductor device may include plurality of capacitors each including a one of the lower electrodes, a dielectric film, and an upper electrode. An upper end of the capacitor support pad is below the upper ends of the lower electrodes. A portion of the stripe-shaped capacitor support pad is interposed between adjacent ones of lower electrodes included within at least one of the rows and is connected to the adjacent ones of lower electrodes included within the at least one of the rows.

Abstract: In a method of forming a contact structure, first and second conductive structures may be formed on a lower structure to be spaced from each other. An insulating layer may be formed on the lower structure to cover the first and second conductive structures. A first hole exposing the first conductive structure may be formed through the insulating layer. A spacer may be formed on a sidewall of the first hole. A first contact electrically coupled to the first conductive structure may be formed in the first hole having the sidewall on which the spacer is formed. A portion of the insulating layer located between the spacers may be removed to form a second hole exposing the second conductive structure. A second contact electrically coupled to the second conductive structure may be formed in the second hole.

Abstract: An insulation interlayer having first contact holes exposing first contact pads is formed on a semiconductor structure having the first and second contact pads. Conductive patterns connected to the first contact pads through the first contact holes are formed on the insulation interlayer. Insulation layer patterns are formed on the insulation interlayer and the conductive patterns. The conductive patterns and the insulation layer patterns extend in different directions. Portions of the insulation layers, exposed between the conductive patterns and the insulation layer patterns, are etched to form second contact holes exposing the second contact pads. Capping patterns are formed on portions of the insulation layer patterns, exposed between the insulation layer patterns, and side faces of the second contact holes. Contact plugs electrically connected to the second contact pads are formed between the capping patterns and the contact plugs.

Abstract: A method of manufacturing a semiconductor device may involve providing a first insulation pattern on a substrate including first and second regions. The first insulation pattern may include a first contact hole for exposing the first region. A spacer may be provided on a sidewall of the first insulation pattern. A conductive pattern may be provided in the first contact hole such that a top surface of the conductive pattern is lower than a top surface of the first insulation pattern. A second insulation pattern may be provided on the conductive pattern. The first insulation pattern may be etched using the second insulation pattern and the spacer as a self-aligning mask to form a second contact hole for exposing the second region. A wring may be provided in the second contact hole.

Abstract: Disclosed is a contact hole forming method capable of reducing parasitic capacitance between a conductive layer patterns, preventing bad contacts caused by mask misalignment and effectively filling an interlayer insulating layer between the conductive layer patterns. The method including forming many conductive layer patterns on a substrate, forming an interlayer insulating layer on a resulting structure where the conductive layer patterns are completed, exposing a conductive layer pattern which at least one sidewall of a contact region between conductive layer patterns is neighboring the contact region, and forming an insulating spacer on the sidewall of the exposed conductive layer pattern.

Abstract: A method for fabricating a semiconductor device capable of minimizing deformations of a photoresist pattern and losses of a hard mask. The method includes the steps of: forming an insulating layer for a hard mask on an etch-target layer; forming a sacrificial layer on the insulating layer; forming a photoresist pattern on the sacrificial layer; forming at least one sacrificial hard mask by etching the sacrificial layer with the photoresist pattern as an etching mask; forming the hard mask by etching the insulating layer with the sacrificial hard mask as an etching mask; and forming a predetermined number of patterns by etching the etch-target layer with use of the sacrificial hard mask and the hard mask as etching masks.

Abstract: In an embodiment, a method of forming a capacitor for a semiconductor device of which structural stability is improved is shown. Cylindrical storage electrodes are formed in a matrix pattern on a substrate that includes an insulation interlayer having contacts therein so that a mold layer surrounds the cylindrical storage electrodes. Sacrificial plugs are formed with a cap within these electrodes. A stabilizing layer is formed on the etched mold layer and the cylindrical storage electrode by partially etching the mold layer. The stabilizing layer is etched until the sacrificial plug is exposed, thereby forming a spacer. While the sacrificial plug and the mold layer are fully removed, the spacer is partially removed, thereby forming a stabilizing member for supporting neighboring storage electrodes adjacent to each other. Accordingly, a structural stability of the capacitor is improved.

Abstract: A method for manufacturing a semiconductor memory device includes the steps of forming a mask layer on a target layer to be etched, coating a photoresist on the mask layer, exposing the photoresist by using a light resource whose wavelength is of about 157 nm to 193 nm, forming a photoresist pattern by developing the photoresist, forming a mask pattern by selectively etching the mask layer with an etching gas except of fluorine-based gases by using the photoresist pattern as an etching mask; and selectively etching the target layer by using the mask pattern as an etching mask.

Abstract: A method for fabricating a semiconductor device capable of minimizing deformations of a photoresist pattern and losses of a hard mask. The method includes the steps of: forming an insulating layer for a hard mask on an etch-target layer; forming a sacrificial layer on the insulating layer; forming a photoresist pattern on the sacrificial layer; forming at least one sacrificial hard mask by etching the sacrificial layer with the photoresist pattern as an etching mask; forming the hard mask by etching the insulating layer with the sacrificial hard mask as an etching mask; and forming a predetermined number of patterns by etching the etch-target layer with use of the sacrificial hard mask and the hard mask as etching masks.

Abstract: A method for manufacturing a semiconductor memory device includes the steps of forming a mask layer on a target layer to be etched, coating a photoresist on the mask layer, exposing the photoresist by using a light resource whose wavelength is of about 157 nm to 193 nm, forming a photoresist pattern by developing the photoresist, forming a mask pattern by selectively etching the mask layer with an etching gas except of fluorine-based gases by using the photoresist pattern as an etching mask; and selectively etching the target layer by using the mask pattern as an etching mask.

Abstract: Disclosed is a contact hole forming method capable of reducing parasitic capacitance between a conductive layer patterns, preventing bad contacts caused by mask misalignment and effectively filling an interlayer insulating layer between the conductive layer patterns. The method including forming many conductive layer patterns on a substrate, forming an interlayer insulating layer on a resulting structure where the conductive layer patterns are completed, exposing a conductive layer pattern which at least one sidewall of a contact region between conductive layer patterns is neighboring the contact region, and forming an insulating spacer on the sidewall of the exposed conductive layer pattern.