Abstract: An N-channel output stage having low substrate current injection during a standby mode includes a first transistor having a drain coupled to a source of supply voltage and a second transistor having a drain coupled to the source of the first transistor and a source for driving a load in a normal operating mode. A pair of multiplexers are respectively coupled to the gate of the first and second transistors. The multiplexers turn on the first transistor and couple an input signal to the gate of the second transistor in the normal operating mode, and couple a predetermined bias voltage to the gate of the first transistor and turn off the second transistor in a standby mode. The value of the bias voltage is selected to be approximately equal to VTOTAL/2+VT, wherein VTOTAL is equal to the total voltage across the output stage in the standby mode and VT is an N-channel threshold voltage.

Abstract: An improved CMOS voltage level translator circuit having an interface stage, an intermediate stage and an output stage is presented. The inventive circuit is characterized by low crossover current in the output and intermediate stages while maintaining minimal delay response when translating a lower potential signal into a higher potential signal. The improved translator circuit may be used in applications such as during EEPROM programming where control signals with normal voltage TTL voltage swing of V.sub.CC and V.sub.SS need to interface with the EEPROM row decoders which require a much higher voltage swing of V.sub.CC ' (>V hd CC) and V.sub.SS.

Abstract: A CMOS intermediate potential generation circuit having a voltage reference state, an intermediate comparator stage and an output stage. The intermediate potential is also used as feedback to the comparator stage. The inventive circuit is characterized by low standby current consumption, quick correction to deviations in the output voltage due to load variations, and quick response to generate a new intermediate potential relative to transitions of voltage supplies.

Abstract: A bandgap voltage reference employing only subsurface currents wich may be fabricated using a standard CMOS process. The reference includes first and second vertical bipolar transistors having common collectors formed in an integrated circuit substrate. A first resistor connects the emitter of the first transistor to ground potential. A second resistor connects the emitter of the second transistor to a reference node while a third resistor connects the reference node to ground. A differential amplifier has a positive input connected to the reference node, a negative input connected to the first transistor emitter and an output connected to the bases of the first and second transistors and also providing the reference voltage output. In a preferred form the output of the differential amplifier is buffered by a third transistor and coupled by a resistive divider to the first and second transistor bases so that the reference voltage may be selected at any scalar of the basic bandgap voltage.