Patents by Inventor Kulanthaivelu Veluchamy Balamurugan

Kulanthaivelu Veluchamy Balamurugan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7991819
    Abstract: The binary coded decimal (BCD) adder circuit adds two BCD encoded operands, with an input carry bit, and produces a BCD encoded sum. The adder has three stages. The first stage receives two BCD encoded operands as inputs, groups the inputs into contiguous blocks of 4-bits each, computes an intermediate sum vector and carry vector without considering the input carry bit, and also computes propagation and generate functions for each 4-bit group. The second stage is a carry look ahead circuit which computes all carries from the input carry, and the propagate and generate functions of the 4-bit groups from the first stage. The third stage adjusts the intermediate sum vector with pre-correction factors which depend upon the input carry and the carries generated from the second stage and the carry vectors from the first stage.
    Type: Grant
    Filed: September 26, 2007
    Date of Patent: August 2, 2011
    Assignee: International Business Machines Corporation
    Inventors: Neelamekakannan Alagarsamy, Kulanthaivelu Veluchamy Balamurugan
  • Patent number: 7299254
    Abstract: The binary coded decimal (BCD) adder circuit adds two BCD encoded operands, with an input carry bit, and produces a BCD encoded sum. The adder has three stages. The first stage receives two BCD encoded operands as inputs, groups the inputs into contiguous blocks of 4-bits each, computes an intermediate sum vector and carry vector without considering the input carry bit, and also computes propagation and generate functions for each 4-bit group. The second stage is a carry look ahead circuit which computes all carries from the input carry, and the propagate and generate functions of the 4-bit groups from the first stage. The third stage adjusts the intermediate sum vector with pre-correction factors which depend upon the input carry and the carries generated from the second stage and the carry vectors from the first stage.
    Type: Grant
    Filed: November 24, 2003
    Date of Patent: November 20, 2007
    Assignee: International Business Machines Corporation
    Inventors: Neelamekakannan Alagarsamy, Kulanthaivelu Veluchamy Balamurugan