Patents by Inventor Kulbhushan Thakur

Kulbhushan Thakur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Hitless switching when generating an output clock derived from multiple redundant input clocks
    Patent number: 10514720
    Abstract: A phase locked loop (PLL) includes a multiplexer (MUX), a phase detector, a filter block, an oscillator, a frequency divider, and a clock switch controller, and achieves hitless switching between a primary clock and a redundant clock. The clock switch controller, upon detecting a condition requiring switching from the primary clock to the redundant clock, is operable to restart the feedback divider synchronously with respect to the redundant clock, and derive the output of the PLL from the redundant clock. The PLL further includes a delay block to process delayed phase error signals generated by the phase detector. The PLL performs hitless clock switching in the event of input clock loss or in response to a command to switch input clocks. The PLL further includes circuitry for estimating and cancelling residual phase errors.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: December 24, 2019
    Assignee: Aura Semiconductor Pvt. Ltd
    Inventors: Raja Prabhu J, Ankit Seedher, Augusto Marques, Srinath Sridharan, Kulbhushan Thakur
  • HITLESS SWITCHING WHEN GENERATING AN OUTPUT CLOCK DERIVED FROM MULTIPLE REDUNDANT INPUT CLOCKS
    Publication number: 20190384351
    Abstract: A phase locked loop (PLL) includes a multiplexer (MUX), a phase detector, a filter block, an oscillator, a frequency divider, and a clock switch controller, and achieves hitless switching between a primary clock and a redundant clock. The clock switch controller, upon detecting a condition requiring switching from the primary clock to the redundant clock, is operable to restart the feedback divider synchronously with respect to the redundant clock, and derive the output of the PLL from the redundant clock. The PLL further includes a delay block to process delayed phase error signals generated by the phase detector. The PLL performs hitless clock switching in the event of input clock loss or in response to a command to switch input clocks. The PLL further includes circuitry for estimating and cancelling residual phase errors.
    Type: Application
    Filed: May 22, 2019
    Publication date: December 19, 2019
    Applicant: Aura Semiconductor Pvt. Ltd
    Inventors: Raja Prabhu J, Ankit Seedher, Augusto Marques, Srinath Sridharan, Kulbhushan Thakur