Abstract: Methods and apparatus to perform efficient indirect branch prediction operations are described. In one embodiment, a branch target buffer (BTB) stored a target address and a bimodal hysteresis counter for an indirect branch that has been encountered by a front-end of the processor during a time period. An indirect branch prediction logic then generates a prediction for an instruction corresponding to a indirect branch based on the stored bimodal hysteresis counter of the BTB. Other embodiments are also claimed and disclosed.

Abstract: Methods and apparatus relating to dynamic selection of execution stage are described. In some embodiments, logic may determine whether to execute an instruction at one of a plurality of stages in a processor. In some embodiments, the plurality of stages are to at least correspond to an address generation stage or an execution stage of the instruction. Other embodiments are also described and claimed.