Patents by Inventor Kuljeet Singh

Kuljeet Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220292386
    Abstract: Embodiments of this disclosure include a method and system for machine learning based evaluation of user experience on information technology (IT) support service. The method may include obtaining a field data of an IT support service ticket and obtaining a multi-score prediction engine. The method may further include predicting metric scores of a plurality of IT support service metrics for the support service ticket based on the field data by executing the multi-score prediction engine. The method may further include obtaining system-defined weights and user-defined weights for the plurality of service metrics and calculating a support service score for the support service ticket based on the metric scores, the system-defined weights, and the user-defined weights. The method may further include evaluating user experience based on the support service score.
    Type: Application
    Filed: March 9, 2021
    Publication date: September 15, 2022
    Inventors: Madhan Kumar Srinivasan, Kishore Kumar Gajula, Gagan Deep Khosla, Kuljeet Singh, Ashish Pant
  • Patent number: 7282796
    Abstract: An electronic assembly is described, having a substrate and contacts on the substrate which are spaced and arranged in a manner that allows for a more dense arrangement of contacts but still allows for routing of traces between the contacts.
    Type: Grant
    Filed: November 18, 2004
    Date of Patent: October 16, 2007
    Assignee: Intel Corporation
    Inventors: Kuljeet Singh, Kevin E. Wells, Julius Delino
  • Patent number: 7247517
    Abstract: A semiconductor die having a through via formed therein is disclosed. A first conductive layer is formed on the front side of the die and a second conductive layer is formed on the backside of the die, and coupled with the through via. A first package substrate is electrically coupled with the first conductive layer, and a second package substrate is electrically coupled with the second conductive layer. In another embodiment, a substrate ball electrically couples the first and second package substrates. In a further embodiment, a flip chip bump is attached to the first package substrate.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: July 24, 2007
    Assignee: Intel Corporation
    Inventors: Christopher L. Rumer, Kuljeet Singh
  • Patent number: 7064431
    Abstract: An electronic assembly is described, having a substrate and contacts on the substrate which are spaced and arranged in a manner that allows for a more dense arrangement of contacts but still allows for routing of traces between the contacts.
    Type: Grant
    Filed: November 18, 2004
    Date of Patent: June 20, 2006
    Assignee: Intel Corporation
    Inventors: Kuljeet Singh, Kevin E. Wells, Julius Delino
  • Publication number: 20050087858
    Abstract: An electronic assembly is described, having a substrate and contacts on the substrate which are spaced and arranged in a manner that allows for a more dense arrangement of contacts but still allows for routing of traces between the contacts.
    Type: Application
    Filed: November 18, 2004
    Publication date: April 28, 2005
    Inventors: Kuljeet Singh, Kevin Wells, Julius Delino
  • Publication number: 20050090125
    Abstract: An electronic assembly is described, having a substrate and contacts on the substrate which are spaced and arranged in a manner that allows for a more dense arrangement of contacts but still allows for routing of traces between the contacts.
    Type: Application
    Filed: November 18, 2004
    Publication date: April 28, 2005
    Inventors: Kuljeet Singh, Kevin Wells, Julius Delino
  • Patent number: 6885102
    Abstract: An electronic assembly is described, having a substrate and contacts on the substrate which are spaced and arranged in a manner that allows for a more dense arrangement of contacts but still allows for routing of traces between the contacts.
    Type: Grant
    Filed: August 26, 2002
    Date of Patent: April 26, 2005
    Assignee: Intel Corporation
    Inventors: Kuljeet Singh, Kevin E. Wells, Julius Delino
  • Publication number: 20050067714
    Abstract: A semiconductor die having a through via formed therein is disclosed. A first conductive layer is formed on the front side of the die and a second conductive layer is formed on the backside of the die, and coupled with the through via. A first package substrate is electrically coupled with the first conductive layer, and a second package substrate is electrically coupled with the second conductive layer. In another embodiment, a substrate ball electrically couples the first and second package substrates. In a further embodiment, a flip chip bump is attached to the first package substrate.
    Type: Application
    Filed: September 30, 2003
    Publication date: March 31, 2005
    Inventors: Christopher Rumer, Kuljeet Singh
  • Publication number: 20040192019
    Abstract: The present invention relates to a device that includes a low-ohmic test. The device includes a metallization copper pad such as metal-six, a metal first film such as Ni that is disposed above the metallization copper pad, and a metal second film such as Au that is disposed above the metal first film. The present invention also relates to a wire-bonding process, and to a method of pulling a first wire bond and making a second wire bond.
    Type: Application
    Filed: April 5, 2004
    Publication date: September 30, 2004
    Applicant: Intel Corporation
    Inventors: Krishna Seshan, Kuljeet Singh
  • Patent number: 6764877
    Abstract: An apparatus and method for dissipating static electrical charge following a manufacturing operation is disclosed. A semiconductor package is provided with ground pads that are located to assure electrical contact with ejection pins used to translate the package from one position to another. Static electricity builds up on the semiconductor package. The ejection pins provide the pathway for dissipating static electrical charge out of the semiconductor package.
    Type: Grant
    Filed: February 25, 2003
    Date of Patent: July 20, 2004
    Assignee: Intel Corporation
    Inventors: Arthur K. Lin, Robert A. Anderson, Kuljeet Singh
  • Patent number: 6715663
    Abstract: The present invention relates to a device that includes a low-ohmic test. The device includes a metallization copper pad such as metal-six, a metal first film such as Ni that is disposed above the metallization copper pad, and a metal second film such as Au that is disposed above the metal first film. The present invention also relates to a wire-bonding process, and to a method of pulling a first wire bond and making a second wire bond.
    Type: Grant
    Filed: January 16, 2002
    Date of Patent: April 6, 2004
    Assignee: Intel Corporation
    Inventors: Krishna Seshan, Kuljeet Singh
  • Publication number: 20040036176
    Abstract: An electronic assembly is described, having a substrate and contacts on the substrate which are spaced and arranged in a manner that allows for a more dense arrangement of contacts but still allows for routing of traces between the contacts.
    Type: Application
    Filed: August 26, 2002
    Publication date: February 26, 2004
    Inventors: Kuljeet Singh, Kevin E. Wells, Julius Delino
  • Publication number: 20030137038
    Abstract: An apparatus and method for dissipating static electrical charge following a manufacturing operation is disclosed. A semiconductor package is provided with ground pads that are located to assure electrical contact with ejection pins used to translate the package from one position to another. Static electricity builds up on the semiconductor package. The ejection pins provide the pathway for dissipating static electrical charge out of the semiconductor package.
    Type: Application
    Filed: February 25, 2003
    Publication date: July 24, 2003
    Inventors: Arthur K. Lin, Robert A. Anderson, Kuljeet Singh
  • Publication number: 20030132766
    Abstract: The present invention relates to a device that includes a low-ohmic test. The device includes a metallization copper pad such as metal-six, a metal first film such as Ni that is disposed above the metallization copper pad, and a metal second film such as Au that is disposed above the metal first film. The present invention also relates to a wire-bonding process, and to a method of pulling a first wire bond and making a second wire bond.
    Type: Application
    Filed: January 16, 2002
    Publication date: July 17, 2003
    Applicant: Intel Corporation
    Inventors: Krishna Seshan, Kuljeet Singh
  • Patent number: 6566741
    Abstract: An apparatus and method for dissipating static electrical charge following a manufacturing operation is disclosed. A semiconductor package is provided with ground pads that are located to assure electrical contact with ejection pins used to translate the package from one position to another. Static electricity builds up on the semiconductor package. The ejection pins provide the pathway for dissipating static electrical charge out of the semiconductor package.
    Type: Grant
    Filed: October 21, 1999
    Date of Patent: May 20, 2003
    Assignee: Intel Corporation
    Inventors: Arthur K. Lin, Robert A. Anderson, Kuljeet Singh
  • Publication number: 20020105064
    Abstract: An apparatus and method for dissipating static electrical charge following a manufacturing operation is disclosed. A semiconductor package is provided with ground pads that are located to assure electrical contact with ejection pins used to translate the package from one position to another. Static electricity builds up on the semiconductor package. The ejection pins provide the pathway for dissipating static electrical charge out of the semiconductor package.
    Type: Application
    Filed: October 21, 1999
    Publication date: August 8, 2002
    Inventors: ARTHUR K. LIN, ROBERT A. ANDERSON, KULJEET SINGH
  • Patent number: 6404067
    Abstract: An integrated circuit package including a substrate, an integrated circuit, and an encapsulant. The substrate has two opposing surfaces and an opening that extends between the two surfaces. The integrated circuit is mounted to the substrate substantially centered over the opening such that a portion of the opening is left uncovered by the integrated circuit. The encapsulant encapsulates the integrated circuit with a portion of the encapsulant extending between the two surfaces of the substrate and attached to the lower surface of the integrated circuit.
    Type: Grant
    Filed: July 19, 2000
    Date of Patent: June 11, 2002
    Assignee: Intel Corporation
    Inventors: Kuljeet Singh, Joseph C. Barrett
  • Patent number: 6129241
    Abstract: A pill dispenser that is disposed in a handle of a toothbrush includes an auger mechanism constructed so that one complete turn of a dispensing knob causes the dispenser to eject a single pill from a port. The dispensing knob includes a safety mechanism that requires the knob to be pushed inward to engage the auger mechanism. The housing of the device, the toothbrush handle, is constructed so as to be waterproof so that no water is introduced to the pills in the dispenser. The ejection port is sealed so that there is no water introduction through the port. In addition, there is a labelling means provided so that the user can easily track the daily ingestion of the pills.
    Type: Grant
    Filed: February 10, 1999
    Date of Patent: October 10, 2000
    Inventor: Kuljeet Singh Rai
  • Patent number: 6050585
    Abstract: A bicycle seat power adjustment mechanism includes a two-direction activation switch mounted on the handlebars and a power supply mounted on the bike frame or under the seat. The power supply would typically be a battery pack, and may be used in conjunction with a generator powered by the motion of the bicycle. An electric motor drives a bevel gear combination that causes an interior drive shaft to rotate. The drive shaft is contained within the seat mounting post and a receiving member of the bike frame. The drive shaft is threaded so that, depending upon the direction of rotation, the drive shaft is moved up and down within a seat post receiving member of the bicycle frame. The direction of rotation is controlled by the activation switch. A rotation inhibition mechanism is provided so that the seat does not tend to rotate when the device is activated.
    Type: Grant
    Filed: December 23, 1998
    Date of Patent: April 18, 2000
    Inventor: Kuljeet Singh Rai