Patents by Inventor Kultaransingh Hooghan

Kultaransingh Hooghan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060068218
    Abstract: The electrical and mechanical properties of structures such as lead frames and other electrical/electronic devices containing, during processing, copper/tin interfaces are improved by introduction of nickel to such interface. Typically, a weight percentage of nickel to tin in the range 1 to 12 weight percent yields upon melting of the tin, an intermetallic compound with essentially no occluded, unbound tin. Thus undesirable anomalous structures such as tin needles and substantially non-planar interface compositions are avoided. Advantageously a nickel/tin/copper intermetallic interface that is substantially planar is formed in the substantial absence of needle-like tin structures.
    Type: Application
    Filed: September 28, 2004
    Publication date: March 30, 2006
    Inventors: Kultaransingh Hooghan, John Osenbach, Brian Potteiger, Poopa Ruengsinsub, Richard Shook, Prakash Suratkar, Brian Vaccaro
  • Publication number: 20060028340
    Abstract: The present invention provides an apparatus and method for detecting if a person has attempted to tamper with an integrated circuit (IC). The apparatus is located on the IC and comprises detection circuitry that detects a build up of electrical charge on the IC and disablement circuitry that disables the IC when the detection circuitry detects a build up of electrical charge on the IC. The method comprises detecting if a build up of electrical charge on the IC has occurred and disabling the IC when a build up of electrical charge on the IC has been detected.
    Type: Application
    Filed: August 4, 2004
    Publication date: February 9, 2006
    Inventors: Kultaransingh Hooghan, James Cargo, Charles Berthoud, Scott McLellan, Kouros Azimi
  • Publication number: 20050090071
    Abstract: A semiconductor chip and method of fabrication which permits precise location of hidden areas of the chip. At least two alignment marks are formed in or on the top passivation layer to provide topological features for location of the hidden areas. The hidden areas can then be selectively etched and/or added to, for example, by a focused ion beam for repair or other functions.
    Type: Application
    Filed: October 28, 2003
    Publication date: April 28, 2005
    Inventors: Joseph Dower, Kultaransingh Hooghan