Patents by Inventor Kultaransingh N. Hooghan

Kultaransingh N. Hooghan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Alignment marking for rock sample analysis
    Patent number: 9552958
    Abstract: A method for using a Focused Ion Beam and/or Scanning Electron Microscope (FIB/SEM) for etching one or more alignment markers on a rock sample, the one or more alignment markers being etched on the rock sample using the FIB/SEM. The one or more alignment markers may further be deposited with a platinum alloy or other suitable compositions for increasing alignment marker visibility.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: January 24, 2017
    Assignee: Weatherford Technology Holdings, LLC
    Inventor: Kultaransingh N. Hooghan
  • Alignment Marking for Rock Sample Analysis
    Publication number: 20150243471
    Abstract: A method for using a Focused Ion Beam and/or Scanning Electron Microscope (FIB/SEM) for etching one or more alignment markers on a rock sample, the one or more alignment markers being etched on the rock sample using the FIB/SEM. The one or more alignment markers may further be deposited with a platinum alloy or other suitable compositions for increasing alignment marker visibility.
    Type: Application
    Filed: February 25, 2014
    Publication date: August 27, 2015
    Applicant: Weatherford/Lamb, Inc.
    Inventor: Kultaransingh N. Hooghan
  • Whisker-free lead frames
    Patent number: 8013428
    Abstract: A method of fabricating an interconnection between a region of copper material and a conducting region is disclosed. The method includes a step of forming a region of tin material and a step of forming a region of nickel material. The method also includes a step of melting the tin material to induce formation of a nickel/tin/copper intermetallic composition at an interface between the region of copper material and the conducting region. The region of tin material and the region of nickel material define the interface between the region of copper material and the conducting region.
    Type: Grant
    Filed: July 28, 2009
    Date of Patent: September 6, 2011
    Assignee: LSI Corporation
    Inventors: Kultaransingh N. Hooghan, John W. Osenbach, Brian Dale Potteiger, Poopa Ruengsinsub, Richard L. Shook, Prakash Suratkar, Brian T. Vaccaro
  • Whisker-free lead frames
    Publication number: 20090291321
    Abstract: A method of fabricating an interconnection between a region of copper material and a conducting region is disclosed. The method includes a step of forming a region of tin material and a step of forming a region of nickel material. The method also includes a step of melting the tin material to induce formation of a nickel/tin/copper intermetallic composition at an interface between the region of copper material and the conducting region. The region of tin material and the region of nickel material define the interface between the region of copper material and the conducting region.
    Type: Application
    Filed: July 28, 2009
    Publication date: November 26, 2009
    Applicant: LSI Corporation
    Inventors: Kultaransingh N. Hooghan, John W. Osenbach, Brian Dale Potteiger, Poopa Ruengsinsub, Richard L. Shook, Prakash Suratkar, Brian T. Vaccaro
  • Method and apparatus for disabling an integrated circuit (IC) when an attempt is made to bypass security on the IC
    Patent number: 7202782
    Abstract: The present invention provides an apparatus and method for detecting if a person has attempted to tamper with an integrated circuit (IC). The apparatus is located on the IC and comprises detection circuitry that detects a build up of electrical charge on the IC and disablement circuitry that disables the IC when the detection circuitry detects a build up of electrical charge on the IC. The method comprises detecting if a build up of electrical charge on the IC has occurred and disabling the IC when a build up of electrical charge on the IC has been detected.
    Type: Grant
    Filed: August 4, 2004
    Date of Patent: April 10, 2007
    Assignee: Agere Systems Inc.
    Inventors: Kultaransingh N. Hooghan, James T. Cargo, Charles W. Berthoud, Scott W. McLellan, Kouros Azimi
  • Fabricating semiconductor chips
    Patent number: 6975040
    Abstract: A semiconductor chip and method of fabrication which permits precise location of hidden areas of the chip. At least two alignment marks are formed in or on the top passivation layer to provide topological features for location of the hidden areas. The hidden areas can then be selectively etched and/or added to, for example, by a focused ion beam for repair or other functions.
    Type: Grant
    Filed: October 28, 2003
    Date of Patent: December 13, 2005
    Assignee: Agere Systems Inc
    Inventors: Joseph P. Dower, Kultaransingh N. Hooghan