Patents by Inventor Kum-Weng Loo

Kum-Weng Loo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8013438
    Abstract: A semiconductor package includes a substrate board and a semiconductor die attached to a top surface of that substrate board. A heat spreader is provided over the semiconductor die. A stiffening ring is positioned surrounding the semiconductor die, the stiffening ring being attached to the top surface of the substrate board and attached to a bottom surface of the plate portion of the heat spreader. Space is left on the board outside of the stiffening ring to support the installation of passive components to the substrate board. An external ring may be included, with that external ring being interconnected to the stiffening ring by a set of tie bars. Alternatively, the heat spreader includes an integrally formed peripheral sidewall portion.
    Type: Grant
    Filed: July 21, 2009
    Date of Patent: September 6, 2011
    Assignee: STMicroelectronics Asia Pacific Pte. Ltd.
    Inventors: Jing-En Luan, Kum-Weng Loo
  • Patent number: 7919361
    Abstract: The present disclosure provides a very thin semiconductor package including a leadframe with a die-attach pad and a plurality of lead terminals, a die attached to the die-attach pad and electrically connected to the lead terminals via bonding wires, a position member disposed upon the die and/or die-attach pad, and a molding material encapsulating the leadframe, the die, and the position member together to form the semiconductor package. The method for manufacturing a very thin semiconductor package includes disposing a first position member on one side of the die-attach pad of a leadframe, attaching a die onto the opposite side of the die-attach pad, optionally disposing a second position member on top of the die, electrically connecting the die to the lead terminals of the leadframe, and encapsulating the leadframe, the die, and the position member(s) together to form the very thin semiconductor package.
    Type: Grant
    Filed: May 19, 2010
    Date of Patent: April 5, 2011
    Assignee: STMicroelectronics Asia Pacific Pte. Ltd.
    Inventors: Kum-weng Loo, Chek-lim Kho, Jing-en Luan
  • Publication number: 20110018125
    Abstract: A semiconductor package includes a substrate board and a semiconductor die attached to a top surface of that substrate board. A heat spreader is provided over the semiconductor die. A stiffening ring is positioned surrounding the semiconductor die, the stiffening ring being attached to the top surface of the substrate board and attached to a bottom surface of the plate portion of the heat spreader. Space is left on the board outside of the stiffening ring to support the installation of passive components to the substrate board. An external ring may be included, with that external ring being interconnected to the stiffening ring by a set of tie bars. Alternatively, the heat spreader includes an integrally formed peripheral sidewall portion.
    Type: Application
    Filed: July 21, 2009
    Publication date: January 27, 2011
    Applicant: STMicroelectronics Asia Pacific PTE LTD (Singapore)
    Inventors: Kum-Weng Loo, Jing-En Luan
  • Publication number: 20110006411
    Abstract: A multichip integrated circuit apparatus includes first and second integrated circuit die mounted on opposite sides of a leadframe die paddle, with at least one of the integrated circuit die extending further toward the leads than does the die paddle. With this arrangement, the active circuit areas of both integrated circuit die can face in the same direction, and can be wire bonded to the same surfaces of the leads. This avoids wire bonding complications that are often encountered in multichip integrated circuit package designs.
    Type: Application
    Filed: September 14, 2010
    Publication date: January 13, 2011
    Applicant: STMicroelectronics Asia Pacific Pte. Ltd.
    Inventors: Kum-Weng Loo, Chek-Lim Kho
  • Publication number: 20100297813
    Abstract: The present disclosure provides a very thin semiconductor package including a leadframe with a die-attach pad and a plurality of lead terminals, a die attached to the die-attach pad and electrically connected to the lead terminals via bonding wires, a position member disposed upon the die and/or die-attach pad, and a molding material encapsulating the leadframe, the die, and the position member together to form the semiconductor package. The method for manufacturing a very thin semiconductor package includes disposing a first position member on one side of the die-attach pad of a leadframe, attaching a die onto the opposite side of the die-attach pad, optionally disposing a second position member on top of the die, electrically connecting the die to the lead terminals of the leadframe, and encapsulating the leadframe, the die, and the position member(s) together to form the very thin semiconductor package.
    Type: Application
    Filed: May 19, 2010
    Publication date: November 25, 2010
    Applicant: STMICROELECTRONICS ASIA PACIFIC PTE LTD
    Inventors: Kum-weng Loo, Chek-lim Kho, Jing-en Luan
  • Patent number: 7816182
    Abstract: A multichip integrated circuit apparatus includes first and second integrated circuit die mounted on opposite sides of a leadframe die paddle, with at least one of the integrated circuit die extending further toward the leads than does the die paddle. With this arrangement, the active circuit areas of both integrated circuit die can face in the same direction, and can be wire bonded to the same surfaces of the leads. This avoids wire bonding complications that are often encountered in multichip integrated circuit package designs.
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: October 19, 2010
    Assignee: STMicroelectronics Asia Pacific Pte. Ltd.
    Inventors: Kum-Weng Loo, Chek-Lim Kho
  • Patent number: 7745945
    Abstract: The present disclosure provides a very thin semiconductor package including a leadframe with a die-attach pad and a plurality of lead terminals, a die attached to the die-attach pad and electrically connected to the lead terminals via bonding wires, a position member disposed upon the die and/or die-attach pad, and a molding material encapsulating the leadframe, the die, and the position member together to form the semiconductor package. The method for manufacturing a very thin semiconductor package includes disposing a first position member on one side of the die-attach pad of a leadframe, attaching a die onto the opposite side of the die-attach pad, optionally disposing a second position member on top of the die, electrically connecting the die to the lead terminals of the leadframe, and encapsulating the leadframe, the die, and the position member(s) together to form the very thin semiconductor package.
    Type: Grant
    Filed: October 10, 2006
    Date of Patent: June 29, 2010
    Assignee: STMicroelectronics Asia Pacific Pte. Ltd.
    Inventors: Kum-weng Loo, Chek-lim Kho, Jing-en Luan
  • Publication number: 20070085177
    Abstract: The present disclosure provides a very thin semiconductor package including a leadframe with a die-attach pad and a plurality of lead terminals, a die attached to the die-attach pad and electrically connected to the lead terminals via bonding wires, a position member disposed upon the die and/or die-attach pad, and a molding material encapsulating the leadframe, the die, and the position member together to form the semiconductor package. The method for manufacturing a very thin semiconductor package includes disposing a first position member on one side of the die-attach pad of a leadframe, attaching a die onto the opposite side of the die-attach pad, optionally disposing a second position member on top of the die, electrically connecting the die to the lead terminals of the leadframe, and encapsulating the leadframe, the die, and the position member(s) together to form the very thin semiconductor package.
    Type: Application
    Filed: October 10, 2006
    Publication date: April 19, 2007
    Applicant: STMICROELECTRONICS ASIA PACIFIC PTE LTD
    Inventors: Kum-weng Loo, Chek-lim Kho, Jing-en Luan
  • Patent number: 7056765
    Abstract: A semiconductor package having a substrate; a semiconductor die attached to the substrate; a housing attached to the substrate and arranged to surround the semiconductor die; and solidified molding material arranged around the housing and adhering to the substrate to secure the housing in position on the substrate. A method of manufacturing the package is also disclosed.
    Type: Grant
    Filed: November 13, 2003
    Date of Patent: June 6, 2006
    Assignee: STMicroelectronics Asia Pacific Pte Ltd.
    Inventors: Kum-Weng Loo, Chek-Lim Kho
  • Publication number: 20060113643
    Abstract: A multichip integrated circuit apparatus includes first and second integrated circuit die mounted on opposite sides of a leadframe die paddle, with at least one of the integrated circuit die extending further toward the leads than does the die paddle. With this arrangement, the active circuit areas of both integrated circuit die can face in the same direction, and can be wire bonded to the same surfaces of the leads. This avoids wire bonding complications that are often encountered in multichip integrated circuit package designs.
    Type: Application
    Filed: November 30, 2004
    Publication date: June 1, 2006
    Applicant: STMicroelectronics Asia Pacific Pte. Ltd.
    Inventors: Kum-Weng Loo, Chek-Lim Kho
  • Publication number: 20040159927
    Abstract: A semiconductor package having a substrate; a semiconductor die attached to the substrate; a housing attached to the substrate and arranged to surround the semiconductor die; and solidified molding material arranged around the housing and adhering to the substrate to secure the housing in position on the substrate. A method of manufacturing the package is also disclosed.
    Type: Application
    Filed: November 13, 2003
    Publication date: August 19, 2004
    Applicant: STMicroelectronics Asia Pacific Pte Ltd
    Inventors: Kum-Weng Loo, Chek-Lim Kho