Patents by Inventor Kum Woh Vincent Leong

Kum Woh Vincent Leong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Structure and method to form source and drain regions over doped depletion regions
    Patent number: 7888752
    Abstract: A structure and method of reducing junction capacitance of a source/drain region in a transistor. A gate structure is formed over on a first conductive type substrate. We perform a doped depletion region implantation by implanting ions being the second conductive type to the substrate using the gate structure as a mask, to form a doped depletion region beneath and separated from the source/drain regions. The doped depletion regions have an impurity concentration and thickness so that the doped depletion regions are depleted due to a built-in potential creatable between the doped depletion regions and the substrate. The doped depletion region and substrate form depletion regions between the source/drain regions and the doped depletion region. We perform a S/D implant by implanting ions having a second conductivity type into the substrate to form S/D regions. The doped depletion region and depletion regions reduce the capacitance between the source/drain regions and the substrate.
    Type: Grant
    Filed: February 14, 2007
    Date of Patent: February 15, 2011
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: King Jien Chui, Francis Benistant, Ganesh Shamkar Samudra, Kian Meng Tee, Yisuo Li, Kum Woh Vincent Leong, Kheng Chok Tee
  • Structure and method to form source and drain regions over doped depletion regions
    Patent number: 7202133
    Abstract: A structure and method of reducing junction capacitance of a source/drain region in a transistor. A gate structure is formed over on a first conductive type substrate. We perform a doped depletion region implantation by implanting ions being the second conductive type to the substrate using the gate structure as a mask, to form a doped depletion region beneath and separated from the source/drain regions. The doped depletion regions have an impurity concentration and thickness so that the doped depletion regions are depleted due to a built-in potential creatable between the doped depletion regions and the substrate. The doped depletion region and substrate form depletion regions between the source/drain regions and the doped depletion region. We perform a S/D implant by implanting ions having a second conductivity type into the substrate to form S/D regions. The doped depletion region and depletion regions reduce the capacitance between the source/drain regions and the substrate.
    Type: Grant
    Filed: January 21, 2004
    Date of Patent: April 10, 2007
    Assignee: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: King Jien Chui, Francis Benistant, Ganesh Shamkar Samudra, Kian Meng Tee, Yisuo Li, Kum Woh Vincent Leong, Kheng Chok Tee