Patents by Inventor Kumar Abhishek Singh

Kumar Abhishek Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250102744
    Abstract: Technologies for fiber array unit (FAU) lid designs are disclosed. In one embodiment, channels in the lid allow for suction to be applied to fibers that the lid covers, pulling the fibers into place in a V-groove. The suction can hold the fibers in place as the fiber array unit is mated with a photonic integrated circuit (PIC) die. Additionally or alternatively, channels can be on pitch, allowing for pulling the FAU towards a PIC die as well as sensing the position and alignment of the FAU to the PIC die. In another embodiment, a warpage amount of a PIC die is characterized, and a FAU lid with a similar warpage is fabricated, allowing for the FAU to position fibers correctly relative to waveguides in the PIC die. In another embodiment, a FAU has an extended lid, which can provide fiber protection as well as position and parallelism tolerance control.
    Type: Application
    Filed: September 27, 2023
    Publication date: March 27, 2025
    Applicant: Intel Corporation
    Inventors: Feifei Cheng, Kumar Abhishek Singh, Peter A. Williams, Ziyin Lin, Fan Fan, Yang Wu, Saikumar Jayaraman, Baris Bicen, Darren Vance, Anurag Tripathi, Divya Pratap, Stephanie J. Arouh
  • Patent number: 11545407
    Abstract: An integrated circuit package may be formed having at least one heat dissipation structure within the integrated circuit package itself. In one embodiment, the integrated circuit package may include a substrate; at least one integrated circuit device, wherein the at least one integrated circuit device is electrically attached to the substrate; a mold material on the substrate and adjacent to the at least one integrated circuit device; and at least one heat dissipation structure contacting the at least one integrated circuit, wherein the at least one heat dissipation structure is embedded either within the mold material or between the mold material and the substrate.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: January 3, 2023
    Assignee: Intel Corporation
    Inventors: Kumar Abhishek Singh, Omkar Karhade, Nitin Deshpande, Mitul Modi, Edvin Cetegen, Aastha Uppal, Debendra Mallik, Sanka Ganesan, Yiqun Bai, Jan Krajniak, Manish Dubey, Ravindranath Mahajan, Ram Viswanath, James C. Matayabas, Jr.
  • Publication number: 20220390694
    Abstract: The removal of heat from silicon photonic integrated circuit devices is a significant issue in integrated circuit packages. As presented herein, the removal of heat may be facilitated with an optically compatible thermal interface structure on the silicon photonic integrated circuit device. These thermal interface structures may include stack-up designs, comprising an optical isolation structure and a thermal interface material, which reduces light coupling effects, while effectively conducting heat from the silicon photonic integrated circuit device to a heat dissipation device, thereby allowing effective management of the temperature of the silicon photonic integrated circuit device.
    Type: Application
    Filed: June 4, 2021
    Publication date: December 8, 2022
    Applicant: Intel Corporation
    Inventors: Chia-Pin Chiu, Kaveh Hosseini, Thu Ngoc Tran, Yew Fatt Kok, Kumar Abhishek Singh, Xiaoqian Li, Marely Tejeda Ferrari, Ravindranath Mahajan, Kevin Ma, Casey Thielen
  • Patent number: 11462527
    Abstract: Embodiments disclosed herein include an electronics package. In an embodiment, the electronics package comprises a package substrate and a die on the package substrate. In an embodiment, a mold layer is positioned over the package substrate. In an embodiment, the electronics package further comprises through-mold interconnects through the mold layer, and a trench that extends at least partially into the mold layer.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: October 4, 2022
    Assignee: Intel Corporation
    Inventors: Kumar Abhishek Singh, Zhaozhi Li, Thomas J. Debonis, Robert Nickerson, Rees Winters
  • Publication number: 20200227332
    Abstract: An integrated circuit package may be formed having at least one heat dissipation structure within the integrated circuit package itself. In one embodiment, the integrated circuit package may include a substrate; at least one integrated circuit device, wherein the at least one integrated circuit device is electrically attached to the substrate; a mold material on the substrate and adjacent to the at least one integrated circuit device; and at least one heat dissipation structure contacting the at least one integrated circuit, wherein the at least one heat dissipation structure is embedded either within the mold material or between the mold material and the substrate.
    Type: Application
    Filed: January 10, 2019
    Publication date: July 16, 2020
    Applicant: Intel Corporation
    Inventors: Kumar Abhishek Singh, Omkar Karhade, Nitin Deshpande, Mitul Modi, Edvin Cetegen, Aastha Uppal, Debendra Mallik, Sanka Ganesan, Yiqun Bai, Jan Krajniak, Manish Dubey, Ravindranath Mahajan, Ram Viswanath, James C. Matayabas, JR.
  • Publication number: 20200035658
    Abstract: Embodiments disclosed herein include an electronics package. In an embodiment, the electronics package comprises a package substrate and a die on the package substrate. In an embodiment, a mold layer is positioned over the package substrate. In an embodiment, the electronics package further comprises through-mold interconnects through the mold layer, and a trench that extends at least partially into the mold layer.
    Type: Application
    Filed: July 30, 2018
    Publication date: January 30, 2020
    Inventors: Kumar Abhishek SINGH, Zhaozhi LI, Thomas J. DEBONIS, Robert NICKERSON, Rees WINTERS
  • Publication number: 20170166407
    Abstract: A pick and place machine includes a frame to adjustably mount, in three dimensions, a plurality of vacuum nozzles over a component to be picked according to a first embodiment a multi-head PnP mechanism may be simple and flexible to train for a wide variety of component and package shapes and sizes. Multiple PnP nozzles are staggered independently in three axes. According to a second embodiment, a PnP mechanism uses an array of self-learning nozzles that adapt by adjusting the z height of individual nozzles to the shape of the object to be picked.
    Type: Application
    Filed: December 15, 2015
    Publication date: June 15, 2017
    Inventors: Kumar Abhishek Singh, Pramod Malatkar, Joshua D. Heppner, Jimin Yao