Abstract: In one embodiment, a method is provided for generating dataflow-driven simulation code of a circuit design described with a combination of first and second HDLs. The circuit description is elaborated and a simulation dataflow graph of the circuit description is generated. Simulation code, configured to model execution of the design in a data-driven manner according to the simulation dataflow graph, is generated from the dataflow graph using a first HDL signal representation having a format compatible with the first HDL and a second HDL signal representation having a format compatible with the second HDL. For each instantiated module of the circuit description at a cross language boundary in the simulation dataflow graph, ports of the instantiated module are mapped to the first HDL signal representation and mapped to the second HDL signal representation.

Abstract: One or more embodiments provide a load balancing solution for improving the runtime performance of parallel HDL simulators. During compilation each process is analyzed to determine a simulation cost based on complexity of the HDL processes. During simulation, processes to be executed in the same simulation cycle are scheduled using the simulation costs computed at compile-time in order to reduce the delay incurred during simulation.

Abstract: One or more embodiments provide a method of HDL simulation that determines dependencies, forcing characteristics, and strength characteristics of nets for the entire circuit design during compilation. Simulation code and data structures are generated for each net, individually, based on the determined characteristics of the respective net. As a result, rather than implementing code for simulation of each net capable of handling every possible combination of the characteristics, less complex code and data structures may be generated for simulation of the nets.

Abstract: A method for compiling an HDL specification for simulation includes elaborating the HDL specification and determining singly-driven and multiply-driven nets of the elaborated circuit design. For each singly-driven net, a respective memory location is assigned to store a value of a corresponding driver of the net at runtime. For each multiply-driven net, a contiguous block of memory is assigned to store values of corresponding drivers of the net at runtime. For mixed language designs, this contiguous block contains values for drivers from all HDL languages involved. Simulation code that models the circuit design is generated. For each singly-driven net, the simulation code is configured to store a value of the corresponding driver of the singly-driven net in the respective memory location. For each multiply-driven net, the simulation code is configured to store the values of the corresponding drivers in the assigned block of memory. The generated simulation code is stored.

Abstract: One or more embodiments provide a method of HDL simulation that determines characteristics of nets, such as shorting of nets, non-blocking assignments, etc., for the entire circuit design during compilation. Simulation code and data structures are generated for each net, individually, based on the determined characteristics of the respective net. As a result, rather than implementing code for simulation of each net capable of handling every possible combination of the characteristics, less complex code and data structures may be generated for simulation of the nets.

Abstract: Approaches for generating functions for activating processes in a simulation model. At least two mutually exclusive sub-ranges of a plurality of bits of a net of the circuit design are determined. A respective process set associated with each sub-range of the plurality of bits is determined. The specification of a wakeup function includes for each sub-range of the plurality of bits, a test for a change in value of at least one bit in the sub-range of the plurality of bits, and an initiation of each process in the associated process set in response to a detected change in value of the at least one bit. The specification also includes control, responsive to a detected change in value of at least one bit in one of the sub-ranges, that bypasses a test for a change in value of at least one bit in at least one other of the sub-ranges.

Abstract: Co-simulation platforms generally include a software-based system and a hardware-based system in which different portions of the circuit design are either simulated in a software-based system or emulated on a hardware-based system. Before a model of circuit design can be co-simulated, the circuit design must be transformed and configured into a form that can execute and interface with a specific hardware-based system. The embodiments of the present invention provide a method, system, and article of manufacture for co-simulation of a portion of a circuit design and achieve an advance in the art by improving co-simulation configuration and setup and providing co-simulation adjustment capabilities during runtime.

Abstract: The present interface system includes a controller monitoring pressure on a locomotive brake pipe port, controlling pressure on a train brake pipe port in response to the pressure on a locomotive brake pipe port, providing ECP commands on an ECP trainline via a train electrical terminal in response to the pressure on the locomotive brake pipe port, and providing electrical power on the ECP trainline via an train electrical trainline terminal from the locomotive electrical trainline terminal. The system includes a three position change over valve. The system also includes a wireless display unit which communicates via a transceiver with the controller and displays information from the controller to the operator remote from the interface system.

Abstract: A method of securing a circuit design can include generating a string including a plurality of elements. The plurality of elements can include elements of design information selected from within the circuit design and at least one security element indicating whether the circuit design is protected. The method further can include permuting the plurality of elements of the string, encrypting the permuted string using a key shared with a circuit design tool, and including the permuted and encrypted string within the circuit design.

Abstract: A method of creating a secure intellectual property (IP) representation of a circuit design for use with a software-based simulator can include translating a hardware description language representation of the circuit design into an encrypted intermediate form and compiling the intermediate form of the circuit design to produce encrypted object code. The method further can include linking the encrypted object code with a simulation kernel library thereby creating the secure IP representation of the circuit design. The secure IP can include an encrypted simulation model of the circuit design and a simulation kernel configured to execute the encrypted simulation model.

Abstract: The present interface system includes a controller monitoring pressure on a locomotive brake pipe port, controlling pressure on a train brake pipe port in response to the pressure on a locomotive brake pipe port, providing ECP commands on an ECP trainline via a train electrical terminal in response to the pressure on the locomotive brake pipe port, and providing electrical power on the ECP trainline via an train electrical trainline terminal from the locomotive electrical trainline terminal. The system includes a three position change over valve. The system also includes a wireless display unit which communicates via a transceiver with the controller and displays information from the controller to the operator remote from the interface system.

Abstract: A method of dangling reference detection and garbage collection of VHDL objects within a program includes the steps of providing an Access Value having an Object Reference pointing to an Allocated Object and having and an Access Count pointer pointing to an integer object named Access Count which models a shared access count for the access values. The method sets the Object Reference and the Access Count pointer to null when constructing a new access value and enables an assignment of a negative Access Count to the shared access count when de-allocating a pointer to the Allocated Object. The method also maintains an exact count of a number of pointers pointing to the Allocated Object.

Abstract: An event queue for use with a software-enabled logic simulation tool can include a heap array and a hash table data structure. The heap array can include time slots organized such that each time slot conforms to heap properties which specify, at least in part, that a root node of the array indicates a time slot having a minimum simulation time value. The hash table data structure can include a plurality of entries, wherein selected ones of the entries specify references to at least one of the time slots.

Abstract: A method (900) of modeling transactions and performing inertial rejection can include representing a plurality of scalar signals as one or more transaction objects, wherein each transaction object comprises a start index, an end index, values for each constituent scalar signal which correspond to an index within a range specified by the start index and end index inclusive, and a time at which the values are transacted. (400) The method further can include constructing and adding a new transaction object for the plurality of scalar signals (920) and comparing the new transaction object with at least one existing transaction object (925) wherein the at least one existing transaction object occurs earlier in time than the new transaction object and is within a rejection window. At least one of a start index and an end index of the at least one existing transaction object can be manipulated (975).

Abstract: Method, apparatus, and computer readable medium for simulating an integrated circuit within a modeling system using one or more circuit description language representations of circuitry is described. By example, a circuit description language representation of the one or more circuit description language representations of circuitry is translated into a program language circuit description. A first simulation process is executed and input data is obtained therefrom. A second simulation process is executed with the input data as parametric input to produce output data, the second simulation process being derived from the program language circuit description. The output data produce by the second simulation process is provided to the first simulation process.

Abstract: Method and apparatus for processing a circuit description including a hierarchy of components for logic simulation is described. Each component is described using one of a first hardware description language (HDL) and a second HDL. A root component and each component in the hierarchy below the root component described using an HDL identical to that of the root component is elaborated up to a cross-language boundary. The root component is described using one of the first HDL or the second HDL and each component at the cross-language boundary is described using the other of the first HDL or the second HDL. Each component at the cross-language boundary is stored in one of a first vector associated with the first HDL or a second vector associated with the second HDL based on language. A connection is established between each component at the cross-language boundary and a respective parent component.