Abstract: A bridge in a file server provides a direct link to data storage devices in satisfaction of data requests. The file server has one or more function-specific processors, including network processors (NPs) and file storage processors (FSPs), all operating in parallel and communicating over an interconnect bus. Each FSP is also connected to one or more disk controllers which in turn manage one or more data storage devices. To minimize local bus contention between data storage devices and network communications, separate internal buses are provided in the FSP, one internal bus connected to the interconnect bus for network communications and one internal bus connected to disk controllers for performing I/O operations on data storage devices.

Abstract: The present invention is directed to a novel apparatus for "on-the-fly" data correction and regeneration of a plurality of data read from and stored to a plurality of storage devices. A control circuit is provided for control of data flow to and from the storage devices. The control circuit establishes and maintains a relatively simple semaphore between itself and an interface circuit controlling a FIFO buffer. A mask register is provided as a type of programmable logic AND gate to assert a master ready signal when each of a selected plurality of the interface circuits, one interface circuit per FIFO buffer, indicates that its respective FIFO buffer is ready, either to output or input an entire block. When each is ready, routing and correction commences under control of the control circuit until an entire block has been processed. Each interface circuit includes an associated flip/flop having an output which provides an indication of the ready status.

Abstract: A bridge in a file server provides a direct link to data storage devices in satisfaction of data requests. The file server has one or more function-specific processors, including network processors (NPs) and file storage processors (FSPs), all operating in parallel and communicating over an interconnect bus. Each FSP is also connected to one or more disk controllers which in turn manage one or more data storage devices. To minimize local bus contention between data storage devices and network communications, separate internal buses are provided in the FSP, one internal bus connected to the interconnect bus for network communications and one internal bus connected to disk controllers for performing I/O operations on data storage devices.

Abstract: A modular software control system for an I/O subsystem. A central group of software modules are made to be hardware-independent, with interface modules translating from the host hardware configuration and the I/O subsystem hardware configuration. I/O commands are accomplished using a series of specialized threads, with each thread performing a particular function. An appropriate group of threads are assembled for each I/O command, the group being a "net".

Abstract: The present invention is directed to memory subsystems that use redundant arrays of inexpensive disks (RAID). The subsystem enables dual concurrent accesses to the subsystem buffer by the host and RAID engine, which calculates parity information associated with data being transferred between the host and disk drives, by including a dual-ported staging memory where the host and disk drives are coupled to one port and the RAID engine to the other port. Positioning the RAID engine on the opposite side of the staging memory in relation to the host and disk drives allows for pipelined asynchronous memory subsystem operation, improving system throughput.

Abstract: The present invention provides a method and apparatus for dynamically modifying the priority of access to a bus, where the bus has control and arbitration functions distributed among the devices coupled to the bus, with each device having a fixed priority level. Access to the bus by particular devices is selectively inhibited, preventing them from asserting their fixed priority level. In a preferred embodiment, the present invention provides control over the reselection of a SCSI bus by a plurality of SCSI devices coupled to the bus by providing a pseudo busy signal to SCSI devices from which reselection is not desired. In this fashion, an initiator may issue a plurality of commands to the SCSI devices and control the order in which the devices will be serviced when ready. A plurality of pseudo busy circuits are provided, with one coupled to each device on the bus. Each pseudo busy circuit is controlled by a control signal from the initiator.

Abstract: An improved interface system based in part on the SCSI standard is provided. A single cable data bus simultaneously transfers several bytes of information between two devices. The interface system transfers multiple-byte commands, messages, status information or data in a single parallel transfer. A microsequencer is provided to permit data transfers across the interface without requiring burdensome attention from a processor in a device involved in the transfer.

Abstract: The present invention provides a method and apparatus for dynamically modifying the priority of access to a bus, where the bus has control and arbitration functions distributed among the devices coupled to the bus, with each device having a fixed priority level. Access to the bus by particular devices is selectively inhibited, preventing them from asserting their fixed priority level. In a preferred embodiment, the present invention provides control over the reselection of a SCSI bus by a plurality of SCSI devices coupled to the bus by providing a pseudo busy signal to SCSI devices from which reselection is not desired. In this fashion, an initiator may issue a plurality of commands to the SCSI devices and control the order in which the devices will be serviced when ready. A plurality of pseudo busy circuits are provided, with one coupled to each device on the bus. Each pseudo busy circuit is controlled by a control signal from the initiator.

Abstract: A data storage system having a local processor and a plurality of memory storage elements is used for storing data from one or more external CPUs. The storage system includes a plurality of memory buffers, each coupled to a separate memory storage element. A data path control circuit is programmed by the local processor to control the transfer of data between the external CPUs and the memory buffers. Two interface circuits are coupled between the external CPUs and the memory buffers to provide two data paths for transferring data between the external CPUs and the memory buffers. The data path control circuit contains two independent sequencing circuits for selecting memory buffers. This allows one data path to be used for reading or writing to a number of the memory buffers while the other data path is simultaneously used for a different operation for the rest of the memory buffers.

Abstract: A programmable element sequence selection circuit which selects a repeatable sequence of elements from a plurality of elements is provided. The sequence selection circuit includes a sequence storage circuit into which a sequence of element identifiers is loaded and accessed.

Abstract: A mass memory system for digital computers is disclosed. The system has a plurality of disk drives coupled to a plurality of small buffers. An Error Correction Controller is coupled to a plurality of X-bar switches, the X-bar switches being connected between each disk drive and its buffers. Data is read from and written to the disk drives in parallel and error correction is also performed in parallel. The X-bar switches are used to couple and decouple functional and nonfunctional disk drives to the system as necessary. Likewise, the buffers can be disconnected from the system should they fail. The parallel architecture, combined with a Reed-Solomon error detection and correction scheme and X-bar switches allows the system to tolerate and correct any two failed drives, allowing for high fault-tolerance operation.

Abstract: A method and apparatus for controlling data flow between a computer and a group of memory devices arranged in a particular logical configuration. The system includes a group of first level controllers and a group of second level controllers. The first level controllers and the second level controllers work together such that if one of the second level controllers fails, the routing between the first level controllers and the memory devices is switched to a properly functioning second level controller without the need to involve the computer in the rerouting process. The logical configuration of the memory devices remains constant. The invention also includes switching circuitry which permits a functioning second level controller to assume control of a group of memory devices formerly primarily controlled by the failed second level controller. In addition, the invention provides error check and correction as well as mass storage device configuration circuitry.

Abstract: An improved interface system based in part on the SCSI standard is provided. A single cable data bus simultaneously transfers several bytes of information between two devices. The interface system transfers multiple-byte commands, messages, status information or data in a single parallel transfer. A microsequencer is provided to permit data transfers across the interface without requiring burdensome attention from a processor in a device involved in the transfer.

Abstract: A data storage system having a local processor and a plurality of memory storage elements is used for storing data from one or more external CPUs. The storage system includes a plurality of memory buffers, each coupled to a separate memory storage element. A data path control circuit is programmed by the local processor to control the transfer of data between the external CPUs and the memory buffers. Two interface circuits are coupled between the external CPUs and the memory buffers to provide two data paths for transferring data between the external CPUs and the memory buffers. The data path control circuit contains two independent sequencing circuits for selecting memory buffers. This allows one data path to be used for reading or writing to a number of the memory buffers while the other data path is simultaneously used for a different operation for the rest of the memory buffers.

Abstract: A mass storage apparatus, made up of a plurality of physical storage devices, which is capable of providing both high bandwidth and high operation rate, as necessary, along with high reliability, is provided. The device set is divided into one or more redundancy groups. Each redundancy group is in turn divided into one or more data groups, each of which may span only a small number of the drives in the redundancy group, providing a high request rate, or which may span a large number of drives, providing high bandwidth.

Abstract: A programmable element sequence selection circuit which selects a repeatable sequence of elements from a plurality of elements is provided. The sequence selection circuit includes a sequence storage circuit into which a sequence of element identifiers is loaded and accessed.

Abstract: A method and apparatus for controlling data flow between a computer and a group of memory devices arranged in a particular logical configuration. The system includes a group of first level controllers and a group of second level controllers. The first level controllers and the second level controllers work together such that if one of the second level controllers fails, the routing between the first level controllers and the memory devices is switched to a properly functioning second level controller without the need to involve the computer in the rerouting process. The logical configuration of the memory devices remain constant. The invention also includes switching circuitry which permits a functioning second level controller to assume control of a group of memory devices formerly primarily contolled by the failed second level controller. In addition, the invention provides error check and correction as well as mass storage device configuration circuitry.

Abstract: A mass memory system for digital computers is disclosed. The system has a plurality of disk drives coupled to a plurality of small buffers. An Error Correction Controller is coupled to a plurality of X-bar switches, the X-bar switches being connected between each disk drive and its buffers. Data is read from and written to the disk drives in parallel and error correction is also performed in parallel. The X-bar switches are used to couple and decouple functional and nonfunctional disk drives to the system as necessary. Likewise, the buffers can be disconnected from the system should they fail. The parallel architecture, combined with a Reed-Solomon error detection and correction scheme and X-bar switches allows the system to tolerate and correct any two failed drives, allowing for high fault-tolerance operation.