Patents by Inventor Kumar Ganapathy
Kumar Ganapathy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8370547Abstract: An apparatus includes a printed circuit board with a plurality of printed circuit board traces, a memory controller mounted on the printed circuit board coupled to one or more of the plurality of printed circuit board traces, a plurality of non-volatile type of memory integrated circuits coupled to the printed circuit board, and a plurality of support integrated circuits coupled between the memory controller and the plurality of non-volatile type of memory integrated circuits.Type: GrantFiled: July 6, 2010Date of Patent: February 5, 2013Assignee: Virident Systems, Inc.Inventors: Vijay Karamcheti, Kumar Ganapathy, Kenneth Alan Okin, Rajesh Parekh
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Patent number: 8364867Abstract: A computing system is disclosed that includes a memory controller in a processor socket normally reserved for a processor. A plurality of non-volatile memory modules may be plugged into memory sockets normally reserved for DRAM memory modules. The non-volatile memory modules may be accessed using a data communication protocol to access the non-volatile memory modules. The memory controller controls read and write accesses to the non-volatile memory modules. The memory sockets are coupled to the processor socket by printed circuit board traces. The data communication protocol to access the non-volatile memory modules is communicated over the printed circuit board traces and through the sockets normally used to access DRAM type memory modules.Type: GrantFiled: July 6, 2010Date of Patent: January 29, 2013Assignee: Virident Systems, Inc.Inventors: Vijay Karamcheti, Kumar Ganapathy, Kenneth Alan Okin, Rajesh Parekh
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Publication number: 20130007338Abstract: A memory controller writes to a virtual address associated with data residing within an asymmetric memory component of main memory that is within a computer system and that has a symmetric memory component, while preserving proximate other data residing within the asymmetric memory component. The symmetric memory component within the main memory of the computer system is configured to enable random access write operations in which an address within a block of the symmetric memory component is written without affecting the availability of other addresses within the block of the symmetric memory component during the writing of that address. The asymmetric memory component is configured to enable block write operations in which writing to an address within a region of the asymmetric memory component affects the availability of other addresses within the region of the asymmetric memory component during the block write operations involving the address.Type: ApplicationFiled: September 10, 2012Publication date: January 3, 2013Applicant: VIRIDENT SYSTEMS INC.Inventors: Vijay Karamcheti, Kenneth A. Okin, Kumar Ganapathy, Ashish Singhai, Rajesh Parekh
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Publication number: 20120260030Abstract: A command from an application is received to access a data structure associated with one or more virtual addresses mapped to main memory. A first subset of the virtual addresses for the data structure having constituent addresses that are mapped to the symmetric memory components and a second subset of the virtual addresses for the data structure having constituent addresses that are mapped to the asymmetric memory components are identified. Data associated with the virtual address from the first physical addresses and data associated with the virtual addresses from the second physical addresses are accessed. The data associated with the symmetric and asymmetric memory components is accessed by the application without providing the application with an indication of whether the data is accessed within the symmetric memory component or the asymmetric memory component.Type: ApplicationFiled: June 18, 2012Publication date: October 11, 2012Applicant: VIRIDENT SYSTEMS INC.Inventors: Vijay Karamcheti, Kenneth A. Okin, Kumar Ganapathy, Ashish Singhai, Rajesh Parekh
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Patent number: 8266407Abstract: A memory controller writes to a virtual address associated with data residing within an asymmetric memory component of main memory that is within a computer system and that has a symmetric memory component, while preserving proximate other data residing within the asymmetric memory component. The symmetric memory component within the main memory of the computer system is configured to enable random access write operations in which an address within a block of the symmetric memory component is written without affecting the availability of other addresses within the block of the symmetric memory component during the writing of that address. The asymmetric memory component is configured to enable block write operations in which writing to an address within a region of the asymmetric memory component affects the availability of other addresses within the region of the asymmetric memory component during the block write operations involving the address.Type: GrantFiled: March 22, 2011Date of Patent: September 11, 2012Assignee: Virident Systems Inc.Inventors: Vijay Karamcheti, Kenneth A. Okin, Kumar Ganapathy, Ashish Singhai, Rajesh Parekh
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Publication number: 20120198141Abstract: Data stored within symmetric and asymmetric memory components of main memory is integrated by identifying a first data as having access characteristics suitable for storing in an asymmetric memory component. The first data is included among a collection of data to be written to the asymmetric memory component. An amount of data is identified within the collection of data to be written to the asymmetric memory component. The amount of data is compared within the collection of data to a volume threshold to determine whether a block write to the asymmetric memory component is justified by the amount of data. If justified, the collection of data is loaded to the asymmetric memory component.Type: ApplicationFiled: April 10, 2012Publication date: August 2, 2012Applicant: VIRIDENT SYSTEMS INC.Inventors: Vijay Karamcheti, Kenneth A. Okin, Kumar Ganapathy, Ashish Singhai, Rajesh Parekh
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Publication number: 20120198140Abstract: Main memory is managed by receiving a command from an application to read data associated with a virtual address that is mapped to the main memory. A memory controller determines that the virtual address is mapped to one of the symmetric memory components of the main memory, and accesses memory use characteristics indicating how the data associated with the virtual address has been accessed, The memory controller determines that the data associated with the virtual address has access characteristics suited to an asymmetric memory component of the main memory and loads the data associated with the virtual address to the asymmetric memory component of the main memory. After the loading and using the memory management unit, a command is received from the application to read the data associated with the virtual address, and the data associated with the virtual address is retrieved from the asymmetric memory component.Type: ApplicationFiled: April 10, 2012Publication date: August 2, 2012Applicant: VIRIDENT SYSTEMS INC.Inventors: Vijay Karamcheti, Kenneth A. Okin, Kumar Ganapathy, Ashish Singhai, Rajesh Parekh
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Patent number: 8205061Abstract: A command from an application is received to access a data structure associated with one or more virtual addresses mapped to main memory. A first subset of the virtual addresses for the data structure having constituent addresses that are mapped to the symmetric memory components and a second subset of the virtual addresses for the data structure having constituent addresses that are mapped to the asymmetric memory components are identified. Data associated with the virtual address from the first physical addresses and data associated with the virtual addresses from the second physical addresses are accessed. The data associated with the symmetric and asymmetric memory components is accessed by the application without providing the application with an indication of whether the data is accessed within the symmetric memory component or the asymmetric memory component.Type: GrantFiled: March 15, 2011Date of Patent: June 19, 2012Assignee: Virident Systems Inc.Inventors: Vijay Karamcheti, Kenneth A. Okin, Kumar Ganapathy, Ashish Singhai, Rajesh Parekh
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Patent number: 8156302Abstract: Data stored within symmetric and asymmetric memory components of main memory is integrated by identifying a first data as having access characteristics suitable for storing in an asymmetric memory component. The first data is included among a collection of data to be written to the asymmetric memory component. An amount of data is identified within the collection of data to be written to the asymmetric memory component. The amount of data is compared within the collection of data to a volume threshold to determine whether a block write to the asymmetric memory component is justified by the amount of data. If justified, the collection of data is loaded to the asymmetric memory component.Type: GrantFiled: October 7, 2010Date of Patent: April 10, 2012Assignee: Virident Systems Inc.Inventors: Vijay Karamcheti, Kenneth A. Okin, Kumar Ganapathy, Ashish Singhai, Rajesh Parekh
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Patent number: 8156288Abstract: Main memory is managed by receiving a command from an application to read data associated with a virtual address that is mapped to the main memory. A memory controller determines that the virtual address is mapped to one of the symmetric memory components of the main memory, and accesses memory use characteristics indicating how the data associated with the virtual address has been accessed, The memory controller determines that the data associated with the virtual address has access characteristics suited to an asymmetric memory component of the main memory and loads the data associated with the virtual address to the asymmetric memory component of the main memory. After the loading and using the memory management unit, a command is received from the application to read the data associated with the virtual address, and the data associated with the virtual address is retrieved from the asymmetric memory component.Type: GrantFiled: August 9, 2010Date of Patent: April 10, 2012Assignee: Virident Systems Inc.Inventors: Vijay Karamcheti, Kenneth A. Okin, Kumar Ganapathy, Ashish Singhai, Rajesh Parekh
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Publication number: 20120079181Abstract: A translating memory module is disclosed including a printed circuit board, at least one memory integrated circuit coupled to the printed board, and at least one support chip coupled to the printed circuit board and coupled between the edge connector and the at least one memory integrated circuit. The at least one support chip includes a bi-directional translator to translate between a first memory communication protocol for the at least one memory integrated circuit and a second memory communication protocol for a memory channel differing from the first memory communication protocol. The second memory communication protocol to communicate data, address, and control signals over the memory channel bus to read and write data into the memory of the translating memory module.Type: ApplicationFiled: December 5, 2011Publication date: March 29, 2012Inventors: Kenneth A. Okin, George Moussa, Kumar Ganapathy, Vijay Karamcheti, Rajesh Parekh
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Publication number: 20110320672Abstract: A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.Type: ApplicationFiled: June 28, 2011Publication date: December 29, 2011Inventors: Kumar Ganapathy, Ruban Kanapathippillai, Saurin Shah, George Moussa, Earle F. Philhower, III, Ruchir Shah
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Patent number: 8074022Abstract: A computer system is disclosed including a printed circuit board (PCB) including a plurality of traces, at least one processor mounted to the PCB to couple to some of the plurality of traces, a heterogeneous memory channel including a plurality of sockets coupled to a memory channel bus of the PCB, and a memory controller coupled between the at least one processor and the heterogeneous memory channel. The heterogeneous memory channel includes a plurality of sockets coupled to a memory channel bus of the PCB. The plurality of sockets are configured to receive a plurality of different types of memory modules. The memory controller may be a programmable heterogeneous memory controller to flexibly adapt to the memory channel bus to control access to each of the different types of memory modules in the heterogeneous memory channel.Type: GrantFiled: September 28, 2007Date of Patent: December 6, 2011Assignee: Virident Systems, Inc.Inventors: Kenneth Alan Okin, George Moussa, Kumar Ganapathy, Vijay Karamcheti, Rajesh Parekh
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Patent number: 8051253Abstract: A computer system is disclosed including a printed circuit board (PCB) including a plurality of traces, at least one processor mounted to the PCB to couple to some of the plurality of traces, a heterogeneous memory channel including a plurality of sockets coupled to a memory channel bus of the PCB, and a memory controller coupled between the at least one processor and the heterogeneous memory channel. The heterogeneous memory channel includes a plurality of sockets coupled to a memory channel bus of the PCB. The plurality of sockets are configured to receive a plurality of different types of memory modules. The memory controller may be a programmable heterogeneous memory controller to flexibly adapt to the memory channel bus to control access to each of the different types of memory modules in the heterogeneous memory channel.Type: GrantFiled: September 28, 2007Date of Patent: November 1, 2011Assignee: Virident Systems, Inc.Inventors: Kenneth Alan Okin, George Moussa, Kumar Ganapathy, Vijay Karamcheti, Rajesh Parekh
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Publication number: 20110173371Abstract: A memory controller writes to a virtual address associated with data residing within an asymmetric memory component of main memory that is within a computer system and that has a symmetric memory component, while preserving proximate other data residing within the asymmetric memory component. The symmetric memory component within the main memory of the computer system is configured to enable random access write operations in which an address within a block of the symmetric memory component is written without affecting the availability of other addresses within the block of the symmetric memory component during the writing of that address. The asymmetric memory component is configured to enable block write operations in which writing to an address within a region of the asymmetric memory component affects the availability of other addresses within the region of the asymmetric memory component during the block write operations involving the address.Type: ApplicationFiled: March 22, 2011Publication date: July 14, 2011Applicant: VIRIDENT SYSTEMS INC.Inventors: Vijay Karamcheti, Kenneth A. Okin, Kumar Ganapathy, Ashish Singhai, Rajesh Parekh
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Publication number: 20110167205Abstract: A command from an application is received to access a data structure associated with one or more virtual addresses mapped to main memory. A first subset of the virtual addresses for the data structure having constituent addresses that are mapped to the symmetric memory components and a second subset of the virtual addresses for the data structure having constituent addresses that are mapped to the asymmetric memory components are identified. Data associated with the virtual address from the first physical addresses and data associated with the virtual addresses from the second physical addresses are accessed. The data associated with the symmetric and asymmetric memory components is accessed by the application without providing the application with an indication of whether the data is accessed within the symmetric memory component or the asymmetric memory component.Type: ApplicationFiled: March 15, 2011Publication date: July 7, 2011Applicant: VIRIDENT SYSTEMS INC.Inventors: Vijay Karamcheti, Kenneth A. Okin, Kumar Ganapathy, Ashish Singhai, Rajesh Parekh
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Patent number: 7970961Abstract: A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.Type: GrantFiled: November 11, 2008Date of Patent: June 28, 2011Assignee: Intel CorporationInventors: Kumar Ganapathy, Ruban Kanapathippillai, Saurin Shah, George Moussa, Earle F. Philhower, III, Ruchir Shah
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Patent number: 7930513Abstract: A memory controller writes to a virtual address associated with data residing within an asymmetric memory component of main memory that is within a computer system and that has a symmetric memory component, while preserving proximate other data residing within the asymmetric memory component. The symmetric memory component within the main memory of the computer system is configured to enable random access write operations in which an address within a block of the symmetric memory component is written without affecting the availability of other addresses within the block of the symmetric memory component during the writing of that address. The asymmetric memory component is configured to enable block write operations in which writing to an address within a region of the asymmetric memory component affects the availability of other addresses within the region of the asymmetric memory component during the block write operations involving the address.Type: GrantFiled: November 5, 2007Date of Patent: April 19, 2011Assignee: Virident Systems Inc.Inventors: Vijay Karamcheti, Kenneth A. Okin, Kumar Ganapathy, Ashish Singhai, Rajesh Parekh
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Patent number: 7913055Abstract: A command from an application is received to access a data structure associated with one or more virtual addresses mapped to main memory. A first subset of the virtual addresses for the data structure having constituent addresses that are mapped to the symmetric memory components and a second subset of the virtual addresses for the data structure having constituent addresses that are mapped to the asymmetric memory components are identified. Data associated with the virtual address from the first physical addresses and data associated with the virtual addresses from the second physical addresses are accessed. The data associated with the symmetric and asymmetric memory components is accessed by the application without providing the application with an indication of whether the data is accessed within the symmetric memory component or the asymmetric memory component.Type: GrantFiled: November 5, 2007Date of Patent: March 22, 2011Assignee: Virident Systems Inc.Inventors: Vijay Karamcheti, Kenneth A. Okin, Kumar Ganapathy, Ashish Singhai, Rajesh Parekh
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Publication number: 20110022788Abstract: Data stored within symmetric and asymmetric memory components of main memory is integrated by identifying a first data as having access characteristics suitable for storing in an asymmetric memory component. The first data is included among a collection of data to be written to the asymmetric memory component. An amount of data is identified within the collection of data to be written to the asymmetric memory component. The amount of data is compared within the collection of data to a volume threshold to determine whether a block write to the asymmetric memory component is justified by the amount of data. If justified, the collection of data is loaded to the asymmetric memory component.Type: ApplicationFiled: October 7, 2010Publication date: January 27, 2011Applicant: VIRIDENT SYSTEMS INC.Inventors: Vijay Karamcheti, Kenneth A. Okin, Kumar Ganapathy, Ashish Singhai, Rajesh Parekh