Abstract: A system for providing advertisements with search results in response to a search query comprises a front end and an advertisement server. The front end is configured: to receive a search query; to send a first search request to a search server and sending a first advertisement request to an advertisement server, wherein the first search request includes the search query or information based on the search query, and wherein the first advertisement request includes the search query or information based on the search query and an indication that an advertisement response is not to be provided; to receive search results from the search server; and to send at least some of the search results to the advertisement server in a second advertisement request, wherein the second advertisement request includes an indication that an advertisement response is to be provided.

Abstract: Apparatuses, systems, and methods for low latency parity for a memory device include a controller configured to accumulate, in a memory buffer, combined parity data for a plurality of regions of memory of a memory device in response to write operations for the plurality of regions of memory. The controller is configured to perform a recovery operation for a region of memory in response to determining that a latency setting for the region satisfies a latency threshold. The controller is configured to service a read request for data from the region based on a recovery operation to satisfy the latency setting.

Abstract: Methods, systems, and devices related to domain-based access in a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). The memory array may be organized according to domains, which may refer to various configurations or collections of access lines, and selections thereof, of different portions of the memory array. In various examples, a memory device may determine a plurality of domains for a received access command, or an order for accessing a plurality of domains for a received access command, or combinations thereof, based on an availability of the signal development cache.

Abstract: Examples of the present disclosure describe systems and methods for locating an optimal installation location for an over-the-air (OTA) antenna. In some example aspects, the system described herein may receive a list of preferred local channels and/or programs from a user. The system may then compare those channels and/or programs to at least one database that comprises channel frequencies based on a user's geolocation (e.g., GPS coordinates, address, zip code, etc.). Based on the comparison of the preferred channels and/or programs, the system may suggest a certain installation location of an OTA antenna. The system may evaluate broadcast signals received by the OTA antenna to determine the strength of the signals at the present OTA antenna location. The results of the channel feedback analysis may be displayed in real-time (or near real-time) on a mobile device, indicating to the user if the present location is an optimal installation location.

Abstract: A booming cell start distance and recommended electronic tilt is identified by retrieving a list of cells served by a first base station. A plurality of grids is generated from the first base station to a predetermined threshold distance. A plurality of selected grids is identified between an acceptable coverage limit and a threshold distance. An evaluation is made regarding whether the first base station is not the dominant cell in each of the selected grids based. The number of grids where the first base station is not the dominant cell site is determined based on a dominant carrier threshold. A column of grids where the first base station is no longer the dominant cell site is determined based on the dominant carrier threshold. A bad booming distance of the cell is determined based on the distance from the first base station and the determined column of grids.

Abstract: A serial signal detector and a differential signal detection method are provided. The serial signal detector includes a voltage comparison module and a hybrid logic filter. The voltage comparison module receives a differential signal, including a first shifted signal and a second shifted signal. The voltage comparison module includes a first comparator and a second comparator. Based on the first shifted signal, the second shifted signal, and a voltage threshold, the first and the second comparators respectively generate a first and a second comparison signals. The hybrid logic filter includes a controllable logic gate and a capacitor. The controllable logic gate performs a logic operation related to the first and the second comparison signals and generates a filtered and converted pulse accordingly. The controllable logic gate and the capacitor jointly perform a preliminary filtering operation to the filtered and converted pulse while the logic operation is being performed.

Abstract: Described herein are systems and methods for generating an embedding—a learned representation—for an image. The embedding for the image is derived to capture visual aspects, as well as textual aspects, of the image. An encoder-decoder is trained to generate the visual representation of the image. An optical character recognition (OCR) algorithm is used to identify text/words in the image. From these words, an embedding is derived by performing an average pooling operation on pre-trained embeddings that map to the identified words. Finally, the embedding representing the visual aspects of the image is combined with the embedding representing the textual aspects of the image to generate a final embedding for the image.

Abstract: Disclosed herein is digital object generator that makes uses a one-way function to generate unique digital objects based on the user specific input. Features of the input are first extracted via a few-shot convolutional neural network model, then evaluated weight and integrated fit. The resulting digital object includes a user decipherable output such as a visual representation, an audio representation, or a multimedia representation that includes recognizable elements from the user specific input.

Abstract: Systems and methods are provided for controlling power down of an integrated dual rail memory circuit. The power down system is configured to power down the power rail for input and logic components (VDD) while maintaining power to the power rail for the memory cells (VDDM). The power down system includes two voltage rails, a clock generator, and a power detector for detecting the power on VDD. The power detector generates an isolated power signal when voltage on VDD is below a voltage threshold. The isolated power signal is configured to disable the clock generator and thus reduce dynamic power as the read/write cycle is not triggered during power down.

Abstract: In one embodiment, a device identifies a plurality of access points of a wireless network. The device also identifies a plurality of mobile nodes of a mobile system. The device establishes a first label-switched path in the wireless network that comprises a wireless link between a first mobile node in the plurality of mobile nodes and a first access point in the plurality of access points. The device establishes a second label-switched path in the wireless network that comprises a wireless link between a second mobile node of the mobile system and a second access point in the plurality of access points.

Abstract: Disclosed herein are related to reducing power consumption of a memory device when transitioning from a sleep state to an operational state. In one aspect, the memory device includes a memory cell to store data. In one aspect, the memory device includes an output driver configured to: generate an output signal indicating the stored data, in response to a sleep tracking signal indicating that the memory cell is in the operational state, and generate the output signal having a predetermined voltage irrespective of the stored data, in response to the sleep tracking signal indicating that the memory cell is in the sleep state. In one aspect, the sleep tracking signal is delayed from a sleep control signal causing the memory cell to operate in the sleep state or the operational state.

Abstract: A method of topography determination, the method including: obtaining a first focus value derived from a computational lithography model modeling patterning of an unpatterned substrate or derived from measurements of a patterned layer on an unpatterned substrate; obtaining a second focus value derived from measurement of a substrate having a topography; and determining a value of the topography from the first and second focus values.

Abstract: Circuits and methods are described herein for controlling a bit line precharge circuit. For example, a control circuit includes a first latch circuit and a second latch circuit. The first latch circuit is configured to receive a first light sleep signal. The first latch circuit generates a second light sleep signal according to a clock signal. The second latch circuit is configured to receive the second light sleep signal. The second latch circuit generates a third light sleep signal according to a sense amplifier enable signal. The second latch circuit provides the third light sleep signal to a bit line reading switch, so the bit line reading switch is cutoff after a sense amplifier is enabled.

Abstract: Methods, systems, and devices related to page policies for signal development caching in a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). The memory device may be configured to receive a read command for data stored in the memory array and transfer the data from the memory array to the signal development cache. The memory device may be configured to sense the data using an array of sense amplifiers. The memory device may be configured to write the data from the signal development cache back to the memory array based on one or more policies.

Abstract: Computerized systems and methods are provided to intelligently and dynamically manage a data center comprising at least one server and at least one central manager. The central manager is programmed to access the at least one server on a predetermined schedule to determine whether at least one application is functioning properly by determining a functionality level. Alternatively, the central manager determines whether the at least one server is actively used by determining an activity level for the server. Based on the central manager's determinations, the system dynamically adjusts the power level of the server, resulting in reduced power consumption and a reduction in wasted resources and unnecessary processing power in the management of servers in a data center.

Abstract: A memory circuit includes a global control circuit, a first local control circuit, and a first set of word line post-decoder circuits coupled to a first set of memory cells that is configured to store a first set of data. The global control circuit is configured to generate a first and second set of global pre-decoder signals, and a first set of local address signals. The first local control circuit includes a first set of repeater circuits and a first clock pre-decoder circuit. The first set of repeater circuits is configured to generate a first and second set of local pre-decoder signals in response to the corresponding first and second set of global pre-decoder signals. The first clock pre-decoder circuit is configured to generate a first and second set of clock signals in response to the first set of local address signals and the first clock signal.

Abstract: A booming cell site is identified in a cloud native environment by retrieve an on-air base station from a site database, retrieve a timing advance distribution (TAD) key performance indicator data for a cell site served by the on-air base station from the list, determine a count of configured gaps for the cell site in the timing advance distribution key performance indicator data, determine a count of booming samples that lie beyond the configured count of gaps for the cell site based on the timing advance distribution key performance indicator data, determine a sum of the timing advance distribution key performance indicator data available for the cell site, and determine the percentage of booming cells based on the count of booming samples and the sum of the timing advance distribution key performance indicator.

Abstract: A controller (310) for identifying positioning of an intravascular ultrasound probe (952) includes a memory (362) that stores instructions (884) and a processor (361) that executes the instructions (884). When executed by the processor (361), the instructions (884) cause the controller (310) to execute a process that includes receiving first signals from at least one element of the intravascular ultrasound probe (952). The process also includes receiving second signals from an external ultrasound probe. Based on the first signals and the second signals, the controller (310) determines a position of the intravascular ultrasound probe (952) in a tracking space that includes the intravascular ultrasound probe (952) and the external ultrasound probe.

Abstract: A network device organizes packets into various queues, in which the packets await processing. Queue management logic tracks how long certain packet(s), such as a designated marker packet, remain in a queue. Based thereon, the logic produces a measure of delay for the queue, referred to herein as the “queue delay.” Based on a comparison of the current queue delay to one or more thresholds, various associated delay-based actions may be performed, such as tagging and/or dropping packets departing from the queue, or preventing addition enqueues to the queue. In an embodiment, a queue may be expired based on the queue delay, and all packets dropped. In other embodiments, when a packet is dropped prior to enqueue into an assigned queue, copies of some or all of the packets already within the queue at the time the packet was dropped may be forwarded to a visibility component for analysis.

Abstract: Methods, systems, and devices related to data relocation via a cache are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). In some cases, the memory device may transfer data from a first address of the memory array to the signal development cache. The memory device may transfer the data stored in the signal development cache to a second address of the memory array based on a parameter associated with the first address of the memory array satisfying a criterion for performing data relocation.