Patents by Inventor Kumar Lalgudi

Kumar Lalgudi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200357735
    Abstract: A discrete tapering interconnection is disclosed that forms an interconnection between a first electronic circuit and a second electronic circuit within an integrated circuit. The discrete tapering interconnection includes a first set of multiple parallel conductors situated in a first metal layer of the metal layers of a semiconductor layer stack and a second set of multiple parallel conductors situated in a second metal layer of the metal layers of the semiconductor layer stack. The first set of multiple parallel conductors effectively taper the discrete tapering interconnection as the discrete tapering interconnection traverse between the first electronic circuit and/or the second electronic circuit. This tapering of the discrete tapering interconnection can be an asymmetric tapering or a symmetric tapering. The second set of multiple parallel conductors is arranged to form various interconnections between various parallel conductors from among the first set of multiple parallel conductors.
    Type: Application
    Filed: July 28, 2020
    Publication date: November 12, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jaskirat BINDRA, Kumar LALGUDI
  • Patent number: 10819325
    Abstract: Provided is a selectable delay buffer for tuning a delay path in a circuit. The selectable delay buffer comprises a first delay segment configured to pass an input signal to an output terminal within a first range of time delays, a second delay segment configured to pass the input signal to the output terminal within a second range of time delays that is different from the first range, and a segment selection switch configured to selectively couple the delay segments to the output terminal based on received selection information that indicates which delay segment to couple to the output terminal.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: October 27, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jaskirat Bindra, Kumar Lalgudi
  • Patent number: 10748849
    Abstract: A discrete tapering interconnection is disclosed that forms an interconnection between a first electronic circuit and a second electronic circuit within an integrated circuit. The discrete tapering interconnection includes a first set of multiple parallel conductors situated in a first metal layer of the metal layers of a semiconductor layer stack and a second set of multiple parallel conductors situated in a second metal layer of the metal layers of the semiconductor layer stack. The first set of multiple parallel conductors effectively taper the discrete tapering interconnection as the discrete tapering interconnection traverse between the first electronic circuit and/or the second electronic circuit. This tapering of the discrete tapering interconnection can be an asymmetric tapering or a symmetric tapering. The second set of multiple parallel conductors is arranged to form various interconnections between various parallel conductors from among the first set of multiple parallel conductors.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: August 18, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jaskirat Bindra, Kumar Lalgudi
  • Patent number: 10678990
    Abstract: In some embodiments, an initial circuit arrangement is provided. The initial circuit arrangement includes cells that include default-rule lines and non-default-rule lines. Line widths of the default-rule lines are selectively increased for a first cell in the initial circuit arrangement, thereby providing a first modified circuit arrangement. A first maximum capacitance value is calculated for the first cell of the first modified circuit arrangement. A second modified circuit arrangement is provided by selectively increasing line widths of the non-default-rule lines in the first modified circuit arrangement. A second maximum capacitance value is calculated for the first cell of the second modified circuit arrangement. A line width of a first non-default-rule line is selectively reduced based on whether the first maximum capacitance value adheres to a predetermined relationship with the second maximum capacitance value. The second modified circuit arrangement is manufactured on a semiconductor substrate.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: June 9, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Nan Yang, Chung-Hsing Wang, Yi-Kan Cheng, Kumar Lalgudi
  • Publication number: 20200036368
    Abstract: Provided is a selectable delay buffer for tuning a delay path in a circuit. The selectable delay buffer comprises a first delay segment configured to pass an input signal to an output terminal within a first range of time delays, a second delay segment configured to pass the input signal to the output terminal within a second range of time delays that is different from the first range, and a segment selection switch configured to selectively couple the delay segments to the output terminal based on received selection information that indicates which delay segment to couple to the output terminal.
    Type: Application
    Filed: October 2, 2019
    Publication date: January 30, 2020
    Inventors: Jaskirat Bindra, Kumar Lalgudi
  • Patent number: 10476490
    Abstract: Provided is a selectable delay buffer for tuning a delay path in a circuit. The selectable delay buffer comprises a first delay segment configured to pass an input signal to an output terminal within a first range of time delays, a second delay segment configured to pass the input signal to the output terminal within a second range of time delays that is different from the first range, and a segment selection switch configured to selectively couple the delay segments to the output terminal based on received selection information that indicates which delay segment to couple to the output terminal.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: November 12, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jaskirat Bindra, Kumar Lalgudi
  • Publication number: 20190252309
    Abstract: A discrete tapering interconnection is disclosed that forms an interconnection between a first electronic circuit and a second electronic circuit within an integrated circuit. The discrete tapering interconnection includes a first set of multiple parallel conductors situated in a first metal layer of the metal layers of a semiconductor layer stack and a second set of multiple parallel conductors situated in a second metal layer of the metal layers of the semiconductor layer stack. The first set of multiple parallel conductors effectively taper the discrete tapering interconnection as the discrete tapering interconnection traverse between the first electronic circuit and/or the second electronic circuit. This tapering of the discrete tapering interconnection can be an asymmetric tapering or a symmetric tapering. The second set of multiple parallel conductors is arranged to form various interconnections between various parallel conductors from among the first set of multiple parallel conductors.
    Type: Application
    Filed: April 29, 2019
    Publication date: August 15, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jaskirat BINDRA, Kumar LALGUDI
  • Patent number: 10276497
    Abstract: A discrete tapering interconnection is disclosed that forms an interconnection between a first electronic circuit and a second electronic circuit within an integrated circuit. The discrete tapering interconnection includes a first set of multiple parallel conductors situated in a first metal layer of the metal layers of a semiconductor layer stack and a second set of multiple parallel conductors situated in a second metal layer of the metal layers of the semiconductor layer stack. The first set of multiple parallel conductors effectively taper the discrete tapering interconnection as the discrete tapering interconnection traverse between the first electronic circuit and/or the second electronic circuit. This tapering of the discrete tapering interconnection can be an asymmetric tapering or a symmetric tapering. The second set of multiple parallel conductors is configured and arranged to form various interconnections between various parallel conductors from among the first set of multiple parallel conductors.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jaskirat Bindra, Kumar Lalgudi
  • Publication number: 20190108304
    Abstract: In some embodiments, an initial circuit arrangement is provided. The initial circuit arrangement includes cells that include default-rule lines and non-default-rule lines. Line widths of the default-rule lines are selectively increased for a first cell in the initial circuit arrangement, thereby providing a first modified circuit arrangement. A first maximum capacitance value is calculated for the first cell of the first modified circuit arrangement. A second modified circuit arrangement is provided by selectively increasing line widths of the non-default-rule lines in the first modified circuit arrangement. A second maximum capacitance value is calculated for the first cell of the second modified circuit arrangement. A line width of a first non-default-rule line is selectively reduced based on whether the first maximum capacitance value adheres to a predetermined relationship with the second maximum capacitance value. The second modified circuit arrangement is manufactured on a semiconductor substrate.
    Type: Application
    Filed: November 30, 2018
    Publication date: April 11, 2019
    Inventors: Kuo-Nan Yang, Chung-Hsing Wang, Yi-Kan Cheng, Kumar Lalgudi
  • Publication number: 20190096799
    Abstract: A discrete tapering interconnection is disclosed that forms an interconnection between a first electronic circuit and a second electronic circuit within an integrated circuit. The discrete tapering interconnection includes a first set of multiple parallel conductors situated in a first metal layer of the metal layers of a semiconductor layer stack and a second set of multiple parallel conductors situated in a second metal layer of the metal layers of the semiconductor layer stack. The first set of multiple parallel conductors effectively taper the discrete tapering interconnection as the discrete tapering interconnection traverse between the first electronic circuit and/or the second electronic circuit. This tapering of the discrete tapering interconnection can be an asymmetric tapering or a symmetric tapering. The second set of multiple parallel conductors is configured and arranged to form various interconnections between various parallel conductors from among the first set of multiple parallel conductors.
    Type: Application
    Filed: September 27, 2017
    Publication date: March 28, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jaskirat BINDRA, Kumar Lalgudi
  • Patent number: 10157254
    Abstract: In some embodiments, the present disclosure relates to a clock tree structure disposed on a semiconductor substrate. The clock tree structure includes a first clock line having a first line width and being arranged at a first height as measured from an upper surface of the semiconductor substrate. The clock tree structure also includes a second clock line having a second line width, which differs from the first line width. The second clock line is arranged at a second height as measured from the upper surface of the semiconductor substrate and the second height is equal to the first height. The first line width can be directly proportional to a first current level for the first clock line and the second line width can be directly proportional to a second current level for the second clock line.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Nan Yang, Chung-Hsing Wang, Yi-Kan Cheng, Kumar Lalgudi
  • Publication number: 20180108388
    Abstract: Provided is a selectable delay buffer for tuning a delay path in a circuit. The selectable delay buffer comprises a first delay segment configured to pass an input signal to an output terminal within a first range of time delays, a second delay segment configured to pass the input signal to the output terminal within a second range of time delays that is different from the first range, and a segment selection switch configured to selectively couple the delay segments to the output terminal based on received selection information that indicates which delay segment to couple to the output terminal.
    Type: Application
    Filed: October 18, 2016
    Publication date: April 19, 2018
    Inventors: Jaskirat Bindra, Kumar Lalgudi
  • Patent number: 9799602
    Abstract: An integrated circuit includes: a first spine formed on a first conductive layer of the integrated circuit, the spine runs in a first direction; a first plurality of ribs formed on a second conductive layer of the integrated circuit, the first plurality of ribs run parallel to one another in a second direction that is orthogonal to the first direction and overlap respective portions of the first spine; a first plurality of interlayer vias formed between the first and second conductive layers, each of the plurality of interlayer vias electrically couple respective ones of the first plurality of ribs to the first spine at the respective portions of overlap; and a plurality of signal lines formed on the second conductive layer and running parallel to one another in the second direction.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: October 24, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuang-Hung Chang, Wen-Hao Chen, Yuan-Te Hou, Kumar Lalgudi
  • Publication number: 20170194252
    Abstract: An integrated circuit includes: a first spine formed on a first conductive layer of the integrated circuit, the spine runs in a first direction; a first plurality of ribs formed on a second conductive layer of the integrated circuit, the first plurality of ribs run parallel to one another in a second direction that is orthogonal to the first direction and overlap respective portions of the first spine; a first plurality of interlayer vias formed between the first and second conductive layers, each of the plurality of interlayer vias electrically couple respective ones of the first plurality of ribs to the first spine at the respective portions of overlap; and a plurality of signal lines formed on the second conductive layer and running parallel to one another in the second direction.
    Type: Application
    Filed: December 30, 2015
    Publication date: July 6, 2017
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuang-Hung CHANG, Wen-Hao CHEN, Yuan-Te HOU, Kumar LALGUDI
  • Publication number: 20170186691
    Abstract: In some embodiments, the present disclosure relates to a clock tree structure disposed on a semiconductor substrate. The clock tree structure includes a first clock line having a first line width and being arranged at a first height as measured from an upper surface of the semiconductor substrate. The clock tree structure also includes a second clock line having a second line width, which differs from the first line width. The second clock line is arranged at a second height as measured from the upper surface of the semiconductor substrate and the second height is equal to the first height. The first line width can be directly proportional to a first current level for the first clock line and the second line width can be directly proportional to a second current level for the second clock line.
    Type: Application
    Filed: November 28, 2016
    Publication date: June 29, 2017
    Inventors: Kuo-Nan Yang, Chung-Hsing Wang, Yi-Kan Cheng, Kumar Lalgudi
  • Patent number: 7350174
    Abstract: Layout synthesis of regular structures using relative placement. Relative placement constraint information is received. The relative placement constraint information indicates a relative placement of a plurality of layout objects with respect to each other, wherein at least a first one of the plurality of layout objects may be at a different level of hierarchy in the layout than at least a second one of the plurality of layout objects. The plurality of layout objects is then automatically placed according to the relative placement constraint information.
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: March 25, 2008
    Assignee: Intel Corporation
    Inventors: Vinoo N. Srinivasan, Veerapaneni Nagbhushan, Kumar Lalgudi
  • Publication number: 20050132309
    Abstract: According to some embodiments, a noise problem is automatically analyzed within the context of a cell-based integrated circuit design to identify an adjustment to the design in view of the perturbation to the design caused by the adjustment.
    Type: Application
    Filed: December 16, 2003
    Publication date: June 16, 2005
    Inventors: Prashant Saxena, Kumar Lalgudi
  • Publication number: 20040243963
    Abstract: Layout synthesis of regular structures using relative placement. Relative placement constraint information is received. The relative placement constraint information indicates a relative placement of a plurality of layout objects with respect to each other, wherein at least a first one of the plurality of layout objects may be at a different level of hierarchy in the layout than at least a second one of the plurality of layout objects. The plurality of layout objects is then automatically placed according to the relative placement constraint information.
    Type: Application
    Filed: June 29, 2004
    Publication date: December 2, 2004
    Inventors: Vinoo N. Srinivasan, Veerapaneni Nagbhushan, Kumar Lalgudi
  • Patent number: 6757878
    Abstract: Layout synthesis of regular structures using relative placement. Relative placement constraint information is received. The relative placement constraint information indicates a relative placement of a plurality of layout objects with respect to each other, wherein at least a first one of the plurality of layout objects may be at a different level of hierarchy in the layout than at least a second one of the plurality of layout objects. The plurality of layout objects is then automatically placed according to the relative placement constraint information.
    Type: Grant
    Filed: December 31, 2001
    Date of Patent: June 29, 2004
    Assignee: Intel Corporation
    Inventors: Vinoo N. Srinivasan, Veerapaneni Nagbhushan, Kumar Lalgudi
  • Publication number: 20030126571
    Abstract: Layout synthesis of regular structures using relative placement. Relative placement constraint information is received. The relative placement constraint information indicates a relative placement of a plurality of layout objects with respect to each other, wherein at least a first one of the plurality of layout objects may be at a different level of hierarchy in the layout than at least a second one of the plurality of layout objects. The plurality of layout objects is then automatically placed according to the relative placement constraint information.
    Type: Application
    Filed: December 31, 2001
    Publication date: July 3, 2003
    Inventors: Vinoo N. Srinivasan, Veerapaneni Nagbhushan, Kumar Lalgudi