Abstract: Memory devices having optimized phase change memory (PCM) structures to improve nucleation time variation and methods for forming the phase change memory structures. The PCM structures are composed of layers including a first electrode layer, a PCM layer having a first interface with the first electrode layer comprising a first electrode/PCM interface, and a second electrode layer, having a second interface with the phase change material layer comprising a PCM/second electrode interface. The first electrode/PCM interface and the PCM/second electrode interface are non-flat and configured to reduce statistical variation of nucleation time. Techniques/processes for forming these interfaces include creating serrated or rough edges, forming patterned shapes, and attaching nanodots.

Abstract: A memory device including a memory array comprising a plurality of decks, a respective deck comprising a plurality of memory cells, a respective memory cell comprising a storage element comprising a chalcogenide material; wherein a first deck of the plurality of decks comprises first memory cells with storage elements deposited at a first initial composition of a plurality of elements; and a second deck of the plurality of decks comprises second memory cells with storage elements deposited at a second initial composition of the plurality of elements.

Abstract: A semiconductor device including stacked access device and resistive memory includes a stack disposed on a base structure, the stack including an access device stack and a resistive random-access memory (ReRAM) device stack, sidewall spacers disposed along a portion of the stack, a dielectric layer disposed over the stack, the sidewall spacers and the base structure, and an interlevel dielectric disposed on the dielectric layer.

Abstract: A semiconductor device including stacked access device and resistive memory includes a stack disposed on a base structure, the stack including an access device stack and a resistive random-access memory (ReRAM) device stack, sidewall spacers disposed along a portion of the stack, a dielectric layer disposed over the stack, the sidewall spacers and the base structure, and an interlevel dielectric disposed on the dielectric layer.

Abstract: Embodiments relate to a system, program product, and method for use and an artificial intelligence (AI) platform to identify and analyze physical forces related to sensory input. A sensor operatively coupled to an inertial measurement unit (IMU) is activated. An initial position of the IMU responsive to the sensor activation is captured and movement of the IMU from the initial position is recognized. A comparison is preformed, where the captured initial position is compared to a second position which is correlated with the recognized movement. A score based on the performed comparison is determined and a diagnostic assessment based on the performed comparison and determined score is created. The diagnostic assessment is converted to feedback, where the conversion utilizes real-time communication of an instruction of a second movement position of the IMU. Receipt of the feedback physically conveys a manifestation of the feedback to the apparatus.

Abstract: A memory cell design is disclosed. The design is particularly well-suited for three-dimensional cross-point (3D X-point) memory configurations. Various embodiments of the memory cell design include a stack of layers having a phase change layer or phase change region that includes nitrogen. The presence of the nitrogen increases crystallization rates of the phase change material during transition from an amorphous state to crystalline state, thus increasing the overall speed of the memory device. In some embodiments, the phase change layer includes a small amount of nitrogen homogenously dispersed within the layer. In some other embodiments, the phase change layer includes one or more regions having nitrogen introduced during the deposition process. In some other embodiments, separate material layers that include nitrogen are provided on one or more sides of the phase change layer.

Abstract: A combined semiconductor device is fabricated by forming a first access structure from a mixed ionic electronic conduction (MIEC) material. A first side of a first memory structure is electrically coupled with a first side of the first access structure to form the combination device. A subtractive etching process is applied to the combination device such that a surface of the combination device that is substantially orthogonal to a plane of a substrate of the semiconductor device is within a defined tapering tolerance.

Abstract: A semiconductor device including stacked access device and resistive memory includes a stack disposed on a base structure, the stack including an access device stack and a resistive random-access memory (ReRAM) device stack, sidewall spacers disposed along a portion of the stack, a dielectric layer disposed over the stack, the sidewall spacers and the base structure, and an interlevel dielectric disposed on the dielectric layer.

Abstract: Embodiments relate to a system, program product, and method for use and an artificial intelligence (AI) platform to identify and analyze physical forces related to sensory input. A sensor operatively coupled to an inertial measurement unit (IMU) is activated. An initial position of the IMU responsive to the sensor activation is captured and movement of the IMU from the initial position is recognized. A comparison is preformed, where the captured initial position is compared to a second position which is correlated with the recognized movement. A score based on the performed comparison is determined and a diagnostic assessment based on the performed comparison and determined score is created. The diagnostic assessment is converted to feedback, where the conversion utilizes real-time communication of an instruction of a second movement position of the IMU. Receipt of the feedback physically conveys a manifestation of the feedback to the apparatus.

Abstract: A combined semiconductor device is fabricated by forming a first access structure from a mixed ionic electronic conduction (MIEC) material. A first side of a first memory structure is electrically coupled with a first side of the first access structure to form the combination device. A subtractive etching process is applied to the combination device such that a surface of the combination device that is substantially orthogonal to a plane of a substrate of the semiconductor device is within a defined tapering tolerance.

Abstract: A combined semiconductor device is fabricated by forming a first access structure from a mixed ionic electronic conduction (MIEC) material. A first side of a first memory structure is electrically coupled with a first side of the first access structure to form the combination device. A subtractive etching process is applied to the combination device such that a surface of the combination device that is substantially orthogonal to a plane of a substrate of the semiconductor device is within a defined tapering tolerance.

Abstract: A combined semiconductor device is fabricated by forming a first access structure from a mixed ionic electronic conduction (MIEC) material. A first side of a first memory structure is electrically coupled with a first side of the first access structure to form the combination device. A subtractive etching process is applied to the combination device such that a surface of the combination device that is substantially orthogonal to a plane of a substrate of the semiconductor device is within a defined tapering tolerance.

Abstract: A combined semiconductor device is fabricated by forming a first access structure from a mixed ionic electronic conduction (MIEC) material. A first side of a first memory structure is electrically coupled with a first side of the first access structure to form the combination device. A subtractive etching process is applied to the combination device such that a surface of the combination device that is substantially orthogonal to a plane of a substrate of the semiconductor device is within a defined tapering tolerance.

Abstract: Polyhexahydrotriazine (PHT) film layers are formed by a process comprising heating a first mixture comprising i) a solvent, ii) paraformaldehyde, and iii) a diamine monomer comprising two primary aromatic amine groups at a temperature of about 20° C. to less than 150° C. This heating step forms a stable polyhemiaminal (PHA) in solution, which can be cast on a surface of a substrate, thereby forming an initial film layer comprising the PHA. The initial film layer is heated at a temperature of 180° C. to about 280° C., thereby converting the PHA film layer to a PHT film layer. Young's moduli of about 8 GPA to about 14 GPA have been observed for the PHT film layers.

Abstract: A chromium oxide film is formed at room temperature. The chromium oxide film has at least one partially polycrystalline portion and/or at least one amorphous portion depending upon the substrate(s) over which the chromium oxide film is formed. Partially polycrystalline portion(s) of the chromium oxide film are exposed, at room temperature, to an electron beam that has an accelerating voltage of at least 100 kilovolts to further crystallize the partially polycrystalline portion(s). Amorphous portion(s) of the chromium oxide film are exposed, at room temperature, to an electron beam that has an accelerating voltage of more than 100 kilovolts to crystallize the amorphous portion(s).

Abstract: A method and computer product program for determining Young's modulus. The method includes placing a probe in contact with a surface of a material on a substrate and, with an initial force of 800 nano newtons or less; determining the location of the surface relative to an initial indentation depth for the initial force; increasing the force on the probe from the initial force to a maximum force greater than the initial force to generate a load curve; decreasing the force on the probe from the maximum force to the initial force to generate an unload curve, the maximum force selected such that the unload curve is independent of the presence of the substrate; and using the unload curve, determining a relationship between (i) the reduced modulus of the sample material and (ii) the ratio of probe penetration depth and the thickness of the layer.

Abstract: The present invention relates generally to high current density access devices (ADs), and more particularly, to a structure and method of forming tunable voltage margin access diodes in phase change memory (PCM) blocks using layers of copper-containing mixed ionic-electronic conduction (MIEC) materials. Embodiments of the present invention may use layers MIEC material to form an access device that can supply high current-densities and operate reliably while being fabricated at temperatures that are compatible with standard BEOL processing. By varying the deposition technique and amount of MIEC material used, the voltage margin (i.e. the voltage at which the device turns on and the current is above the noise floor) of the access device may be tuned to specific operating conditions of different memory devices.

Abstract: The present invention relates generally to high current density access devices (ADs), and more particularly, to a structure and method of forming tunable voltage margin access diodes in phase change memory (PCM) blocks using layers of copper-containing mixed ionic-electronic conduction (MIEC) materials. Embodiments of the present invention may use layers MIEC material to form an access device that can supply high current-densities and operate reliably while being fabricated at temperatures that are compatible with standard BEOL processing. By varying the deposition technique and amount of MIEC material used, the voltage margin (i.e. the voltage at which the device turns on and the current is above the noise floor) of the access device may be tuned to specific operating conditions of different memory devices.

Abstract: The present invention relates generally to high current density access devices (ADs), and more particularly, to a structure and method of forming tunable voltage margin access diodes in phase change memory (PCM) blocks using layers of copper-containing mixed ionic-electronic conduction (MIEC) materials. Embodiments of the present invention may use layers MIEC material to form an access device that can supply high current-densities and operate reliably while being fabricated at temperatures that are compatible with standard BEOL processing. By varying the deposition technique and amount of MIEC material used, the voltage margin (i.e. the voltage at which the device turns on and the current is above the noise floor) of the access device may be tuned to specific operating conditions of different memory devices.

Abstract: A device that includes a semiconductor device and a contact electrode with a first side that is opposite a second side. The first side abuts the semiconductor device. The contact electrode has a stoichiometry that varies from the first side to the second side. The stoichiometry of the first side inhibits the diffusion of metal from the semiconductor device into the first contact electrode.