Abstract: Examples relate to managing distribution of a total number of I/O queue pairs of an NVMe target among a plurality of NVM subsystems of the NVMe target and a plurality of hosts connected to the NVMe target. A target controller of the NVMe target defines a number of I/O queue pairs for a dedicated pool and a number of I/O queue pairs for a reserved pool based on the total number of I/O queue pairs. The target controller distributes a number of I/O queue pairs to each of the hosts from the number of I/O queue pairs of the dedicated pool and utilizes the number of I/O queue pairs of the reserved pool to balance out the number of I/O queue pairs on each of the hosts by selectively changing the number of I/O queue pairs of the reserved pool.

Abstract: Examples described herein generally relate to devices that include a pulsed flip-flop capable of being implemented across multiple voltage domains. In an example, a device includes a pulsed flip-flop. The pulsed flip-flop includes a master circuit and a slave circuit sequentially connected to the master circuit. The master circuit includes a pre-charge input circuit and a first latch. A first node is connected between the pre-charge input circuit and the first latch. The slave circuit includes a resolving circuit and a second latch. The first node is connected to an input node of the resolving circuit. A second node is connected between the resolving circuit and the second latch. The resolving circuit is configured to selectively (i) pull up or pull down a voltage of the second node and (ii) be disabled.

Abstract: A circuit includes a master latch circuit and a slave latch circuit. The master latch circuit is configured to receive an input data signal associated with an input data voltage domain and generate a first output data signal associated with an output data voltage domain different from the input data voltage domain. The slave latch circuit is configured to receive, from the master latch circuit, the first output data signal and generate a second output data associated with the output data voltage domain.

Abstract: An integrated circuit (IC) includes an encoder circuit configured to receive input data including a plurality of data bits. A plurality of parity computation equations for a single error correct double error detect adjacent double error correct adjacent triple error detect (SECDEDADECADTED) Hamming code is received. A plurality of parity bits are computed using the plurality of parity computation equations. Write data including the data bits and the parity bits are provided to a write circuit. The write circuit writes the write data to a memory.

Abstract: According to an example, coordination of adjustments to network frame hold time parameters between network devices in a network is initiated based on a trigger condition. Time data may be obtained from a plurality of network devices in the network, where the time data describes a network frame hold time parameter of each network device in the plurality and a network frame processing time of each network device. A set of affected network devices affected by network back pressure in the network, and a set of non-affected network devices in the plurality not included in the set of affected network devices, may be determined. Based on the time data, a pairing may be determined between a time-available network device from the set of non-affected network devices and a time-needed network devices, from the set of affected network devices, to receive an allocation of time credit from the time-available network device.

Abstract: An apparatus includes an encoder circuit block configured to receive input data. The encoder circuit block is configured to generate a plurality of parity bits from the input data and order the input data and the plurality of parity bits to generate encoded data. The encoder circuit block is configured to generate each of the plurality of parity bits based upon selected bits of the input data and orders the input data and the plurality of parity bits so that a decoder circuit block configured to decode the encoded data is able to perform operations including, at least in part, detecting a no bit error, detecting and correcting a single bit error, detecting a double bit error, detecting and correcting an adjacent double bit error, and detecting an adjacent triple bit error. The operations are independent of a number of memory banks used to store the encoded data. The decoder circuit block may also correct an adjacent triple bit error.

Abstract: An integrated circuit (IC) includes an encoder configured to receive input data including a plurality of data bits. The encoder includes a parity computation matrix circuit configured to arrange the data bits according to a matrix format to generate a parity computation matrix. A parity computation circuit is configured to compute a plurality of parity computation row terms corresponding to rows of the parity computation matrix respectively, compute a plurality of parity computation column terms corresponding to columns of the parity computation matrix respectively, and compute parity bits using the parity computation row terms and parity computation column terms. Write data including the data bits and the parity bits are provided to a write circuit. The write circuit writes the write data to a memory cell array in a memory.

Abstract: In an example, a memory circuit in a programmable integrated circuit (IC) includes: a control port and a clock port; a configurable random access memory (RAM) having a control input and a clock input; input multiplexer logic coupled to the control input and the clock input; and a state machine coupled to the input multiplexer logic and configuration logic of the programmable IC, the state machine configured to: in response to being enabled by the configuration logic, control the input multiplexer logic to switch a connection of the control input from the control port to the state machine and, subsequently, switch a connection of the clock input from the clock port to a configuration clock source; and in response to being disabled by the configuration logic, control the input multiplexer logic to switch the connection of the clock input from the configuration clock source to the clock port and, subsequently, switch the connection of the control input from the state machine to the control port.

Abstract: According to an example, coordination of adjustments to network frame hold time parameters between network devices in a network is initiated based on a trigger condition. Time data may be obtained from a plurality of network devices in the network, where the time data describes a network frame hold time parameter of each network device in the plurality and a network frame processing time of each network device. A set of affected network devices affected by network back pressure in the network, and a set of non-affected network devices in the plurality not included in the set of affected network devices, may be determined. Based on the time data, a pairing may be determined between a time-available network device from the set of non-affected network devices and a time-needed network devices, from the set of affected network devices, to receive an allocation of time credit from the time-available network device.

Abstract: An encoder block to receive input data has a KR-Matrix block. The KR-Matrix block is configured to: exclusively OR combinations of subsets of data bits of the input data to generate (n?1) parity bits for n a positive integer greater than zero; and exclusively OR a combination of all of the data bits and all the (n?1) parity bits to generate an (n) parity bit.

Abstract: An embodiment of an apparatus for encoding. For this embodiment of the apparatus, an encoder block is coupled to receive input data. The encoder block has an R-matrix block. The R-matrix block is configured to: exclusively OR combinations of subsets of data bits of the input data to generate (n?1) parity bits for n a positive integer greater than zero; and exclusively OR a combination of all of the data bits and all the (n?1) parity bits to generate an (n) parity bit 9-to-7.