Abstract: A system and method of caching and parameterizing intermediate representation code includes receiving, by a database, a query, parsing, by the database, the query to obtain a plan tree comprising a plurality of plan nodes arranged in hierarchical order descending from a top plan node, generating, by the database, node intermediate representations (IRs) for the plan nodes, executing, by the database, a first query using the node IRs, and reusing, by the database, the node IRs to execute subsequent queries.

Abstract: A method and system for automatic management of dynamically allocated memory in a computer where the system comprises one or more client machines, a communication network and a computer. The one or more users provide one or more queries to access data from the computer and the client machines send the received queries to the computer through the communication network. The processor configured in the computer creates a heap record upon identifying the received queries to be at least one INSERT, DELETE and first type of UPDATE. The heap record is stored in data segment of the one or more databases and when the received queries is second type of UPDATE, the processor creates an undo record and stores the undo record in undo segment of the databases.

Abstract: An integrated circuit test controller and method defining a number N of failure events, applying the test to an integrated circuit under test by applying a predetermined sequence of input and output operations according to a test algorithm. Output data is compared to expected data, and a failure signal is generated when the output data does not correspond to the expected data. If a failure signal is generated, failure data related to the failure event is stored in a failure data register set. If the number N of failure events has been reached or if there are no more tests left, the content of the data failure register set is read out through a parallel failure data output port.

Abstract: An integrated circuit test controller and method defining a number N of failure events, applying the test to an integrated circuit under test by applying a predetermined sequence of input and output operations according to a test algorithm. Output data is compared to expected data, and a failure signal is generated when the output data does not correspond to the expected data. If a failure signal is generated, failure data related to the failure event is stored in a failure data register set. If the number N of failure events has been reached or if there are no more tests left, the content of the data failure register set is read out through a parallel failure data output port.