Patents by Inventor Kumar S. Golla

Kumar S. Golla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7787698
    Abstract: Embodiments of the invention provide an instruction that computes the horizontal and vertical values (H,V) based upon the predefined equations. Based upon the horizontal and vertical values (H,V) and the current sign bit being processed at [m,n], the output context and decision pair (CX,D) is determined placed into a destination register.
    Type: Grant
    Filed: December 19, 2003
    Date of Patent: August 31, 2010
    Assignee: Intel Corporation
    Inventors: Kumar S. Golla, David K. Vavro
  • Patent number: 7565022
    Abstract: A method and apparatus for accelerating the conversion and detecting image data in pixel format into bit-plane format and bit plane format to pixel format for JPEG2000 compression and decompression is disclosed. In one embodiment, a method for encoding coefficients comprises applying one or more wavelet transforms to generate multiple coefficients, converting the pixel coefficients into bit-plane format and detecting zero bit-planes. This causes the image data in pixel to be broken into bit planes and stored in memory. If all the bits in a selected pixel plane are zero, an indication is stored in an N bit memory array corresponding to the N bit planes of the pixel code block that is processed. The indicator bits are useful in speeding up further compression.
    Type: Grant
    Filed: December 19, 2003
    Date of Patent: July 21, 2009
    Assignee: Intel Corporation
    Inventors: Kumar S. Golla, David K. Vavro
  • Patent number: 7565024
    Abstract: Embodiments of the invention provide a run length coding instruction for determining output context and decision values. Pixel coefficient bit values are used after wavelet transformation to determine output context (CX) and decision (D) values. The input is comprised of coefficient bit values (bit1, bit2, bit3, bit 4) in accordance with the scan order and the output are CX and D values. The CX and D pairs are processed together by arithmetic encoder to produce compressed data output (CD). CX selects the probability estimate to use during the coding of D.
    Type: Grant
    Filed: December 19, 2003
    Date of Patent: July 21, 2009
    Assignee: Intel Corporation
    Inventors: Kumar S. Golla, David K. Vavro
  • Patent number: 7095897
    Abstract: When encoding and decoding bit planes, a decision is made in the clean up pass if zero coding or run length coding should be performed. Embodiments of the invention provide a zero coding or run length coding decision instruction. The instruction will determine whether significance state variables associated with selected coefficients bits and their immediate neighbors are zero. If all the significance states are determined to be zero, then run length coding is performed. Else, zero coding is performed.
    Type: Grant
    Filed: December 19, 2003
    Date of Patent: August 22, 2006
    Assignee: Intel Corporation
    Inventors: Kumar S. Golla, David K. Vavro