Abstract: A system and method for emulating single-cycle translation lookaside buffer invalidation are described. One embodiment of a method comprises defining a translation lookaside buffer (TLB) cache marking variable comprising a first marker value and a second marker value. A context bank marker associated with a translation context bank is initiated with one of the first marker value and the second marker value. A TLB cache entry table specifies whether each of a plurality of TLB cache entries associated with the translation context bank has a corresponding entry marker set to the first marker value or the second marker value. In response to a TLB invalidate command associated with the translation context bank, the context bank marker is changed from the one of the first marker value and the second marker value to the other of the first marker value and the second marker value prior to initiating TLB invalidation.

Abstract: A MMU may read page descriptors (using virtual addresses as an index) in a burst mode from page tables in a system memory. The page descriptors may include intermediate physical addresses (“IPAs”, in stage 1) and corresponding physical addresses (“PAs”, in stage 2). The virtual address in conjunction with page table base address register is used to index page descriptors into main memory. The MMU may identify a first group of contiguous IPAs beginning at a base IPA and a second group of contiguous IPAs beginning at an offset from the base IPA. The first and second groups may be separated by at least one IPA not contiguous with either the first or second group. The MMU may read a first PA from the page tables that corresponds to the base IPA. The MMU may store an entry in a buffer that includes the PA and a first linearity tag.